CPU Cache Rail Voting for XR Power and Thermal Limits

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Solution Overview

Problem

Existing XR devices face challenges in minimizing dc power consumption while adhering to stringent thermal constraints, particularly in scenarios where processor and memory voltages exceed nominal levels, leading to inefficient power management and increased temperature.

Innovation Solution

Implementing a two-input AND logical function, a three-input AND logical function, and a two-input OR logical function to determine the optimal selection of processor or memory voltage as the voltage rail for electrical loads, using a multiplexer to manage dc power domains based on voltage comparisons and thresholds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processor and memory voltages are increased above nominal levels, then processing performance is improved, but dc power consumption increases and thermal constraints are violated

Engineering Contradiction:
Improveprocessing performanceVSAvoiddc power consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic voltage rail selection for cache memories, allowing the system to switch between processor voltage rail and memory voltage rail based on real-time operating conditions. This dynamic adaptation enables the system to optimize power consumption at different performance levels while maintaining thermal compliance, directly resolving the contradiction between processing performance and power consumption.

Inventive Principle:
Principle #15Dynamics

2Speed

If processor voltage is increased to improve performance, then processing speed increases, but cache memory power consumption increases due to voltage mismatches

Engineering Contradiction:
Improveprocessing speedVSAvoidcache memory power consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies local quality by providing different voltage rails to different components based on their specific needs. The cache memories can be supplied with either processor voltage or memory voltage depending on the operating scenario, allowing each component to operate at its optimal voltage level. This resolves the energy loss caused by voltage mismatches while maintaining processing speed.

Inventive Principle:
Principle #3Local quality

3Device complexity

If a fixed voltage rail is used for cache memories, then system design is simplified, but power optimization opportunities are lost

Engineering Contradiction:
Improvevoltage rail configurationVSAvoidoverall power consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent introduces dynamic voltage rail selection logic that automatically chooses between processor voltage and memory voltage for cache memories based on real-time conditions. This dynamic approach increases power optimization opportunities while managing complexity through automated control logic, resolving the trade-off between system complexity and power optimization.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12549182B2Optimizing central processing unit (CPU) cache memory DC power with rail voting scheme
Publication Date: 2026.02.10 QUALCOMM INC
  • US12549182B2 patent drawing
  • US12549182B2 patent drawing
  • US12549182B2 patent drawing

AI summary

Aspects of the disclosure are directed to dc power consumption optimization in an extended reality (XR) device with thermal constraints. In accordance with one aspect, the disclosure includes performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.