CPU Instruction Cache Preserving Return Address Data
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Solution Overview
Problem
In CPU architectures, call instructions to sub-routines or interrupt service routines cause discontinuity in processing, leading to performance penalties and increased energy consumption due to the need to discard and re-fetch pre-fetched instructions.
Innovation Solution
A processor with an internal return address and instruction cache that preserves the next N instruction words upon decoding a call instruction, allowing concurrent decoding and execution of these words after completing the sub-routine or ISR, thereby reducing the need for re-fetching from memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If call instructions are executed to sub-routines or interrupt service routines, then the CPU can perform specialized tasks, but processing discontinuity occurs and performance deteriorates due to discarding and re-fetching pre-fetched instructions
Solution Approach 1:
The patent applies preliminary action by pre-fetching and preserving the N instruction words following a call instruction in the instruction pre-fetch buffer before the sub-routine or ISR execution completes. This preserved instruction data is held ready in the buffer, eliminating the need to re-fetch these instructions from external memory after the call returns, thus maintaining processing continuity and reducing time loss.
2Loss of energy
If pre-fetched instructions are discarded during sub-routine execution, then memory space is freed, but energy consumption increases due to re-fetching operations
Solution Approach 1:
The patent performs preliminary action by preserving the N instruction words in the instruction pre-fetch buffer during sub-routine execution. By holding these instructions in the buffer rather than discarding them to memory, the system eliminates the energy-consuming re-fetch operation. The buffer management complexity is minimized by using a fixed-size buffer that automatically overwrites old data when full, requiring no complex allocation or deallocation logic.
3Productivity
If the instruction pre-fetch buffer is used to preserve N instruction words, then re-fetching is eliminated and performance improves, but the buffer requires additional management logic
Solution Approach 1:
The patent ensures continuity of useful action by maintaining the N instruction words in the instruction pre-fetch buffer throughout sub-routine execution. The buffer continuously holds these preserved instructions ready for immediate execution upon return, eliminating idle re-fetch operations. The decode unit concurrently decodes these preserved instructions while the fetch unit fetches new instructions, maintaining continuous productive action without complex management overhead.
Solution Approach 2:
The instruction pre-fetch buffer serves itself by automatically preserving the N instruction words when a call instruction is detected and automatically providing these preserved instructions to the decode unit upon sub-routine return. The buffer management is self-regulating, using simple overwrite-on-full logic that requires no external control or complex management logic, thereby improving throughput without increasing device complexity.
Data Source
AI summary
A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.