Concurrent Instruction Execution TRIZ Cases
- CPU Instruction Cache Preserving Return Address Data
Preserving next N instruction words in the pre-fetch buffer eliminates re-fetching overhead and reduces energy consumption.
- Reconfigurable Processor Instruction Distribution via Memory Sync ID Table
A reconfigurable processor distributes instructions using a memory sync ID table generated from one-hot encoded memory identification fields.
- Packed Instruction Set Architecture for Processor Throughput
A packed instruction set architecture executes multiple data elements simultaneously within a single register to accelerate multimedia and scientific computations.
- Graphics Command Buffer Segmentation for GPU Mode Switching
Segmenting command buffers separates compute shading from 3D rendering, reducing mode transitions and improving GPU resource utilization.
- Multi-Processor Mode Switching Without Reboot
Saves processor context states in memory to synchronize CPUs for lock-step operation, resolving time delay during mode transitions.
- Compiler IF2FOR Transformation for Branch Mispredictions
A compiler applies the IF2FOR transformation to convert conditional branches into segmented loops.
- Video Decoder Assignment for Mobile Devices
A video assignment system allocates streams to hardware decoders based on ranking and type.
- Processor Bounds-Checking Unit for Buffer Overflow Protection
A bounds-checking functional unit in processor cores manages memory buffer address ranges to detect out-of-bounds references during execution.
- Vector Processor On-the-Fly Format Conversion
Load/store unit performs parallel format conversion during data transfer between memory and vector processing elements.
- Workitem Synchronization via Program Counter Segmentation
Segmenting execution flow with independent program counters resolves processing overhead from divergent control flows in heterogeneous computing systems.