Reconfigurable Processor Instruction Distribution via Memory Sync ID Table
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Solution Overview
Problem
Reconfigurable processors face inefficiencies in executing instructions due to limited computing units and dependency relationships among instructions, which hinder parallel execution efficiency and lead to memory conflicts.
Innovation Solution
A method and system that utilize one-hot encoding of memory identification fields to generate a Memory Sync ID Table, establishing dependency relationships among instructions, and executing them in sequence to ensure parallel execution efficiency and reduce memory conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If instructions are executed in sequence due to limited computing units, then resource conflicts are avoided, but execution efficiency deteriorates
Solution Approach 1:
The patent segments instructions into different types (memory access instructions, compute instructions, etc.) and organizes them into separate instruction queues. Each queue handles specific instruction types independently, allowing parallel processing of different instruction types while maintaining resource safety within each queue segment.
Solution Approach 2:
The patent introduces a synchronization control module as an intermediary between instruction queues and computing units. This module manages resource allocation and coordination, enabling efficient parallel execution while preventing resource conflicts through centralized control mechanisms.
2Productivity
If instructions are classified into three types for parallel execution, then execution efficiency improves, but dependency relationships cause efficiency loss
Solution Approach 1:
The patent implements dynamic instruction scheduling where the synchronization control module continuously monitors instruction dependencies and adjusts execution order in real-time. Instructions are dynamically allocated to computing units based on current resource availability and dependency resolution, rather than following a fixed sequence.
Solution Approach 2:
The patent performs preliminary classification and organization of instructions into typed queues before execution. Dependency relationships are analyzed and recorded in advance, allowing the synchronization module to proactively manage execution ordering and minimize waiting time by preparing instruction batches that can be safely executed in parallel.
3Productivity
If memory access instructions are executed without coordination, then instruction throughput increases, but memory conflicts increase
Solution Approach 1:
The synchronization control module acts as an intermediary between memory access instructions and memory resources. It coordinates access patterns, manages memory resource allocation, and prevents conflicts by ensuring that simultaneous memory operations are properly synchronized and ordered.
Solution Approach 2:
The patent implements feedback mechanisms where the synchronization control module monitors memory access patterns and resource utilization. Based on this feedback, it dynamically adjusts instruction scheduling and resource allocation to prevent memory conflicts while maintaining high throughput.
Data Source
AI summary
The disclosure provides a method for distributing instructions in a reconfigurable processor. The reconfigurable processor includes an instruction fetch module, an instruction sync control module and an instruction queue module. The method includes: configuring a format of a Memory Sync ID Table of each instruction type, obtaining a first memory identification field and a second memory identification field of each instruction, obtaining one-hot encodings of first and second memory identification fields, obtaining a sync table and executing each instruction of a plurality of to-be-run instructions.