CPU Pipeline Error Recovery Circuit with Dynamic Mode Selection
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Solution Overview
Problem
Current error recovery approaches for CPU pipelines are limited in their ability to dynamically select an appropriate recovery mode based on system requirements and operating states, leading to suboptimal system throughput and power consumption, especially in applications with wide frequency ranges and high error ratios.
Innovation Solution
An error recovery circuit that integrates on-chip monitoring circuits, an error signal statistics module, a voltage and frequency control module, an error recovery control module, and both local and global error recovery modules, allowing dynamic switching between recovery modes based on error ratios and system states, using a threshold comparison and selection mechanism to optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If local error recovery is used to suspend clock signal for error recovery, then error recovery reliability is improved, but system throughput deteriorates due to frequent clock suspensions
Solution Approach 1:
The patent implements dynamic error recovery mode selection that adapts to system conditions. The controller dynamically switches between local and global error recovery modes based on error frequency and system state, allowing the system to optimize between reliability and throughput in real-time rather than being fixed in one mode
Solution Approach 2:
The system changes operational parameters by adjusting the error recovery strategy based on monitored error ratios and system state. When error ratios are low, the system prefers local recovery to maintain throughput; when error ratios increase, it transitions to global recovery to ensure reliability, thus adapting parameters to balance the contradiction
2Productivity
If global error recovery is used to recover all errors in one operation, then system throughput is improved by reducing recovery operations, but power consumption deteriorates due to extended recovery time
Solution Approach 1:
The system dynamically adjusts the error recovery approach based on real-time monitoring of error ratios and system state. Instead of permanently committing to global recovery, the controller adaptively selects between local and global modes, allowing the system to minimize power consumption by using local recovery when appropriate while still achieving throughput benefits when global recovery is necessary
Solution Approach 2:
The patent applies partial error recovery by using local recovery for individual errors when the error ratio is low, rather than always performing comprehensive global recovery. This partial action approach reduces the excessive power consumption associated with frequent global recovery operations while still maintaining acceptable throughput by handling minor errors locally
3Measurement precision
If on-chip monitoring is used to monitor timing variations in real time, then measurement precision is improved, but device complexity deteriorates due to additional monitoring circuits
Solution Approach 1:
The monitoring function is segmented and distributed across multiple pipeline stages rather than implemented as a single complex centralized monitoring unit. By placing monitoring circuits at specific strategic points in the pipeline and dividing the monitoring task across stages, the system achieves comprehensive timing variation detection while reducing the complexity of any single monitoring component
Solution Approach 2:
The patent introduces an error recovery control module as an intermediary that processes monitoring data and makes recovery decisions. This intermediary layer abstracts the complexity of raw monitoring data interpretation and recovery strategy selection, allowing the monitoring circuits to focus on precise measurement while the control module handles the complexity of decision-making based on that data
Data Source
AI summary
Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.