CPU PLL Stability Measurement Using Clock Frequency Comparison
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Solution Overview
Problem
Existing methods for measuring the stability of a Phase Locked Loop (PLL) in a Central Processing Unit are either expensive, requiring high-bandwidth oscilloscopes, or provide inaccurate results by measuring system stability without directly assessing the PLL.
Innovation Solution
A method using a frequency meter to test the precision of clock signals both with and without passing through the PLL, allowing for a comparison to determine the stability of the PLL without the need for an oscilloscope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an oscilloscope with high bandwidth and active probe is used to measure jitter of output signal, then measurement precision of PLL stability is improved, but device cost and complexity increase
Solution Approach 1:
The patent replaces expensive, complex measurement equipment (high-bandwidth oscilloscope with active probe) with a simple, low-cost frequency meter. This substitution achieves the same measurement objective using inexpensive, readily available equipment, directly resolving the contradiction between measurement precision and device complexity.
Solution Approach 2:
The patent substitutes the electrical measurement system (oscilloscope) with a different approach using a frequency meter that measures frequency rather than time-domain jitter. This substitution transforms the measurement methodology from direct jitter measurement to frequency comparison, achieving PLL stability measurement with simpler equipment.
2Ease of operation
If system stability is measured directly without measuring PLL, then ease of operation is improved, but measurement precision of PLL stability deteriorates
Solution Approach 1:
The patent segments the clock signal path into two separate measurement channels: one measuring the clock signal before PLL processing and another measuring it after PLL processing. By separately measuring both paths and comparing results, the method achieves direct PLL stability measurement while maintaining operational simplicity.
Solution Approach 2:
The patent introduces a comparison mechanism as an intermediary that takes measurements from both signal paths and determines PLL stability by comparing the frequency differences. This intermediary approach enables direct PLL measurement without requiring complex direct measurement equipment, maintaining ease of operation while improving precision.
Data Source
AI summary
The present invention provides a method for measuring an internal Phase Locked Loop of a Central Processing Unit (CPU) by a frequency meter, wherein the method comprises following steps: the (CPU) outputting an oscillation excitation signal to a crystal circuit; the crystal signal generating a clock signal; the internal loop respectively outputting the clock signals that does not pass through and passes through the phase locked loop; adopting a frequency meter to receive the clock signals and perform a clock precision test to correspondingly obtain a first test result and a second result; comparing the first test result and the second result to obtain a result of the stability of the phase locked loop. The beneficial effects of the invention: the operation is simple and it does not need to buy an expensive oscilloscope, the accurate precision of the PLL can be measured without the influence of the crystal.