Crack Stop Structure for Semiconductor Dicing
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Solution Overview
Problem
The use of low-k dielectric materials in semiconductor manufacturing leads to inadequate mechanical strength and adhesion issues, causing cracks during wafer dicing that can degrade IC performance and reliability due to interface de-lamination between low-k dielectric layers.
Innovation Solution
A crack stop structure is formed in the scribe line with a dielectric material-filled trench that penetrates interlayer and intermetal dielectric layers, surrounded by a guard ring and test pads, using materials like porous low-k, polyimide, silicon oxide, or silicon nitride to prevent crack propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are used to reduce RC delay, then interconnect performance is improved, but mechanical strength and adhesion are insufficient causing cracks during dicing
Solution Approach 1:
The patent divides the dielectric structure into multiple segments by introducing crack stop layers between different dielectric layers (e.g., between low-k ILD and FSG/USG). These segmented layers prevent crack propagation across the entire structure, allowing each layer to maintain its functional properties while the overall structure gains crack resistance.
Solution Approach 2:
The patent creates a composite dielectric structure combining low-k dielectric materials with conventional higher-k dielectric materials (FSG, USG) and crack stop layers. This composite approach allows the low-k regions to provide low RC delay while the composite structure as a whole provides enhanced mechanical strength and crack resistance.
2Reliability
If low-k dielectric materials are used, then RC delay is reduced, but adhesion between layers is inadequate causing interface de-lamination during dicing
Solution Approach 1:
The patent introduces crack stop layers as intermediary structures between adjacent dielectric layers. These intermediate layers serve as buffer zones that prevent direct stress transfer between layers during dicing, eliminating the harmful interface de-lamination while maintaining the electrical performance benefits of low-k materials.
Solution Approach 2:
The crack stop layers are positioned in advance between dielectric layers to provide cushioning against mechanical stress during subsequent dicing operations. This beforehand protection prevents interface de-lamination before it can occur during the harmful dicing process.
3Productivity
If wafer dicing is performed to cut semiconductor wafers, then individual IC chips are produced, but cracks extend laterally from dicing lines into the semiconductor and insulating materials
Solution Approach 1:
The patent extracts or removes the continuous dielectric structure at the scribe line regions by introducing crack stop layers that interrupt crack paths. This extraction of continuity in the dielectric layers prevents cracks from propagating laterally from dicing lines into the active circuit regions, while still allowing dicing to proceed for chip production.
Data Source
AI summary
A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.