Crack Stop Trenches in BEOL Layers for Low-k Dielectric Reliability
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Solution Overview
Problem
The use of low-k and ultra-low dielectric constant materials in semiconductor devices leads to poor mechanical properties, causing delamination and reliability issues during chip dicing and packaging, as these materials have poor adhesion to adjacent layers and are prone to cracks and micro-crack propagation.
Innovation Solution
The formation of crack stop trenches around the periphery of semiconductor chips by etching a portion of the BEOL layers, which introduces a gap in the low-k dielectric layers to stop crack propagation and prevent delamination, thereby maintaining chip integrity during dicing and subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low-k and ultra-low dielectric constant materials are used in metallization layers, then interconnect parasitic capacitances are minimized, but mechanical properties deteriorate causing delamination and reliability issues
Solution Approach 1:
The patent divides the continuous low-k dielectric material into segmented regions by introducing crack stop trenches that partition the dielectric into isolated cells. This segmentation prevents crack propagation across the entire structure while maintaining the low-k material's electrical benefits in each localized region.
Solution Approach 2:
The crack stop trenches act as intermediary structures between adjacent low-k dielectric regions. These trenches provide mechanical support and stress relief, preventing direct crack transmission between neighboring dielectric cells while allowing the low-k material to maintain its electrical performance.
2Productivity
If low-k and ultra-low dielectric constant materials are used, then interconnect performance is improved, but adhesion to adjacent layers deteriorates causing delamination
Solution Approach 1:
The continuous dielectric layer is segmented into isolated cells by crack stop trenches, which prevents delamination from propagating across the entire interconnect structure. Each segmented region maintains its adhesion independently, reducing the overall delamination risk.
Solution Approach 2:
The patent applies different structural qualities to different regions: the low-k dielectric material maintains its electrical properties in the cell regions, while the crack stop trenches provide enhanced mechanical strength and adhesion at the boundaries between cells.
3Reliability
If crack stop trenches are formed by etching BEOL layers, then crack propagation is prevented, but device complexity increases
Solution Approach 1:
The crack stop trenches are formed preliminarily during the BEOL manufacturing process before final chip dicing. This preliminary action integrates the crack prevention feature into the existing manufacturing flow without requiring separate post-processing steps.
Solution Approach 2:
The crack stop trenches serve multiple functions: they prevent crack propagation, provide mechanical support to the low-k dielectric, and act as isolation barriers between adjacent cell regions. This multi-functionality reduces the need for additional specialized structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The crack stop trenches effectively minimize crack propagation and delamination, ensuring the reliability and yield of semiconductor components by isolating cracks to the periphery and preserving the integrity of the BEOL layers during chip dicing and packaging processes.
Implementation Method 1
introduces a gap in the low-k dielectric layers to stop crack propagation and prevent delamination
Implementation Method 2
Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions
Data Source
AI summary
Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.