C*RAM Neural Network Power Optimization
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Solution Overview
Problem
Existing C*RAM implementations are inadequate for low-power deep learning applications due to one-dimensional communication limitations, power-hungry eight-bit opcodes, substantial chip area usage by communication buses, inability to perform permutations or table lookups, and reliance on off-chip controllers, which hinder efficient processing of large two-dimensional images and multiple tasks.
Innovation Solution
The implementation of a SIMD controller at the end of a bank of memory with row-select lines, bidirectional multiplexers for ALU operations, segmented buses for efficient data transfer, and decentralized SIMD controllers for each bank of C*RAM, enabling flexible low-resolution arithmetic, power-efficient communications, and local storage and decoding of instructions and coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data is transferred between memory and processing elements in conventional computer architectures, then computations can be performed, but power consumption increases due to the energy required to charge and discharge wiring capacitance over long distances
Solution Approach 1:
The patent merges memory and processing elements into a unified C*RAM architecture where processing elements are embedded directly within the memory structure. This integration eliminates the need for separate memory and processing components, reducing the distance between them and minimizing the energy required for data transfer.
Solution Approach 2:
The patent transitions from conventional one-dimensional memory organization to a two-dimensional array structure where processing elements are embedded at intersections of row and column lines. This dimensional change enables shorter communication paths and more efficient data access patterns, reducing power consumption.
2Adaptability or versatility
If one-dimensional communication is used in C*RAM implementations, then processing elements can be embedded in memory, but the ability to handle large two-dimensional images and perform permutations is limited
Solution Approach 1:
The patent extends communication from one-dimensional to two-dimensional by embedding processing elements at the intersections of row and column lines in a memory array. This enables direct access to two-dimensional data structures and facilitates efficient image processing operations without requiring complex communication structures.
Solution Approach 2:
The patent designs processing elements with universal functionality that can perform various operations including dot products, permutations, and table lookups. This multi-functionality allows the same hardware structure to handle diverse computational tasks, including large two-dimensional image processing, without requiring specialized communication paths.
3Adaptability or versatility
If eight-bit opcodes are used in C*RAM implementations, then a wide variety of operations can be controlled, but substantial chip area is occupied by the opcode and communication buses
Solution Approach 1:
The patent segments the opcode into multiple smaller fields that are transmitted separately through the communication bus. This segmentation reduces the width requirements of the bus while maintaining the ability to control a wide variety of operations, thereby reducing the chip area occupied by communication infrastructure.
Solution Approach 2:
The patent implements a multi-cycle instruction format where opcodes are transmitted over multiple clock cycles rather than in a single wide burst. This periodic transmission reduces the instantaneous bandwidth requirements and allows for narrower communication buses, reducing overall chip area while maintaining full operational control capability.
Data Source
AI summary
A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.