Credit Counters for Reconfigurable Processor Flow Control
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Solution Overview
Problem
Reconfigurable processors, particularly coarse-grained reconfigurable architectures (CGRAs), face challenges in efficiently managing control signaling among processing units, leading to congestion and bottlenecks in data processing operations.
Innovation Solution
A system comprising a compiler and memory that partitions the execution of a dataflow graph into asynchronous stages by inserting stage buffers and creating control connections between them, using credit counters to manage data transmission and prevent congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flow control is implemented in reconfigurable processors, then data transmission efficiency is improved, but control signaling congestion increases
Solution Approach 1:
The flow control mechanism is segmented into distributed counter units at each processing element, with separate control connections for credit signaling. This segmentation allows independent flow control decisions at each node without requiring centralized coordination, reducing control signaling congestion while maintaining efficient data transmission.
Solution Approach 2:
Credit counters act as intermediaries between producers and consumers of data. The counters mediate the flow control by tracking available buffer space and generating appropriate control signals, thereby regulating data transmission efficiency without causing congestion in the control signaling paths.
2Ease of operation
If control connections are added to manage data transmission, then flow control capability is improved, but device complexity increases
Solution Approach 1:
The control connections serve multiple functions: they carry credit signals for flow control, enable buffer management, and coordinate data transmission timing. By making the control connections multi-functional, the system achieves robust flow control capability without proportionally increasing device complexity.
Solution Approach 2:
Each processing element autonomously manages its own flow control through local counters that self-regulate data transmission based on buffer availability. This self-service approach eliminates the need for complex centralized control mechanisms, achieving ease of operation while minimizing device complexity.
Data Source
AI summary
The technology disclosed relates to storing a dataflow graph with a plurality of compute nodes that transmit data between the compute nodes, and controlling data transmission between compute nodes in the plurality of compute nodes based on ready-to-read credit counters and write credit counters. For example, systems and methods according to this disclosure may control data transmission between compute nodes along the data connections between the compute nodes by selectively controlling writing of data based on both the ready-to-read credit counter and the write credit counter of a particular compute node of the plurality of compute nodes.