Credit Return Logic for Chiplet Wide Bus Timing
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Solution Overview
Problem
Existing credit return logic in chiplet-based systems faces design complexity and critical path timing challenges due to the need for additional circuitry and processing cycles for credit management.
Innovation Solution
Implementing a simplified credit return logic that uses a wide bus to transmit multiple flits simultaneously, with only one flit per lane including a credit return value, and employing a bitwise-OR operation to combine credit return data from all received flits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional credit return logic is used in chiplet-based systems, then credit management functionality is provided, but design complexity increases and critical path timing is delayed
Solution Approach 1:
The patent extracts the credit return functionality from the data path by implementing a separate credit return counter and logic unit. The credit return counter is independently configured to count credit return packets, and the credit return logic unit separately determines whether to return credits based on the counted value. This extraction removes the credit management burden from the main data processing path, thereby reducing design complexity while maintaining reliable credit management functionality.
Solution Approach 2:
The patent introduces an intermediary credit return counter between the packet receiver and the credit return decision logic. This counter acts as a mediator that accumulates credit return information over multiple packets before triggering a credit return action. By using this intermediary mechanism, the system avoids complex real-time credit tracking in the critical path while ensuring accurate credit management through the mediating counter's accumulated state.
2Measurement precision
If additional circuitry is added for credit management, then credit tracking accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the credit return counter with an expected credit return value before packet reception begins. The counter is set to trigger a credit return event when the counted credit return packets reach this predetermined value. This preliminary configuration eliminates the need for complex real-time credit tracking circuitry during packet processing, thereby maintaining accurate credit tracking while minimizing additional power consumption from simpler counting logic.
3Manufacturing precision
If complex credit return logic is implemented, then credit management precision is improved, but processing speed decreases
Solution Approach 1:
The patent segments the credit management function into distinct independent components: a credit return counter that simply counts packets, a credit return logic unit that makes binary return decisions, and the main data processing path. Each segment performs a single simple function rather than complex integrated logic. The counter increments for each credit return packet independently of data processing speed, and the logic unit only evaluates the counter value at discrete intervals, thereby maintaining high processing speed while achieving precise credit management through the coordinated segments.
Data Source
AI summary
Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.