Crenellated Metal Lines for Compact IC Layouts

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Solution Overview

Problem

Integrated circuit design faces challenges in optimizing cell library size and density due to strict design rules for metal line spacing and cell boundary distances, limiting the compactness and efficiency of circuit layouts.

Innovation Solution

The implementation of crenellated metal lines, where every other line is made closer to the cell edge, combined with specific placement rules, allows for reduced cell height and increased density by ensuring compliance with design rules for end-to-end and via distances, enabling smaller cells and more devices in less space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal lines are kept at standard distances from cell edges to comply with design rules, then electrical performance is maintained, but cell height increases and density decreases

Engineering Contradiction:
Improveelectrical performanceVSAvoidcell height
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent applies different spacing rules to different metal lines based on their function. Non-power/ground lines are positioned closer to cell edges (first distance) while power/ground lines maintain larger spacing (second distance). This local differentiation allows reduced cell height while maintaining electrical performance for signal lines and providing adequate spacing for power lines.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the cell boundary region into different zones: a first cell boundary region where non-power/ground lines are placed closer to edges, and a second cell boundary region where power/ground lines are placed with larger spacing. This segmentation allows optimized spacing for different line types, reducing overall cell height while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If uniform spacing is used for all metal lines to simplify design, then manufacturing is easier, but cell density and compactness are reduced

Engineering Contradiction:
Improvedesign simplicityVSAvoiddevice density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

Instead of uniform spacing, the patent implements local quality by assigning different spacing characteristics to different metal lines. Non-power/ground lines use one spacing rule (first distance) while power/ground lines use another (second distance), optimizing both density and manufacturability for each line type.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent inverts the conventional approach by not treating all lines uniformly. Rather than applying the more conservative spacing rule to all lines, it applies the relaxed spacing rule specifically to non-power/ground lines where electrical performance allows, while maintaining strict spacing for power/ground lines.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS10490542B2Integrated circuit layout using library cells with alternating conductive lines
Publication Date: 2019.11.26 INTEL CORP
  • US10490542B2 patent drawing
  • US10490542B2 patent drawing
  • US10490542B2 patent drawing

AI summary

An integrated circuit layout is described that uses a library cells with alternating conducting lines. One embodiment includes a first cell and a second cell, the second cell being adjacent to the first cell. The first cell has a first plurality of conductive lines, a first portion of the first plurality having line ends that are a first distance from the second cell. The second cell has a second plurality of conductive lines, the conductive lines being parallel to and aligned with the conductive lines in the first cell, a second portion of the second plurality having line ends that are a second distance from the first cell. The first distance is shorter than the second distance.