Critical Path Validation Circuit for Infeasible IC Timing Tests
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Solution Overview
Problem
Conventional testing circuits fail to validate critical paths in integrated circuits (ICs) due to infeasible excitation, leaving them unvalidated, and require labor-intensive processes with multiple test patterns, increasing validation time and potentially compromising IC safety.
Innovation Solution
A validation circuit is introduced near critical paths, comprising a register circuit, delay circuit, flip-flops, and a comparator, which mimics the critical path's delay and detects deviations using a fault signal, allowing simultaneous validation of multiple paths without interrupting functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing circuits use multiple test patterns to validate critical paths, then validation coverage is improved, but validation time and operational complexity increase significantly
Solution Approach 1:
The patent creates a copy of the critical path using identical circuit components (logic gates, flip-flops, wires) to build a validation circuit that replicates the timing characteristics of the original critical path. This copy allows validation testing without requiring multiple complex test patterns on the actual critical path, thereby reducing validation time while maintaining comprehensive coverage.
Solution Approach 2:
The validation circuit is segmented into distinct functional modules: a delay circuit that replicates critical path delay, a test signal generator, and a comparator. This segmentation allows each module to be independently configured and tested, simplifying the overall validation process and reducing the time required compared to using multiple comprehensive test patterns.
2Reliability
If conventional testing circuits use multiple test patterns to validate critical paths, then validation coverage is improved, but device complexity and operational difficulty increase
Solution Approach 1:
By creating a simplified copy of the critical path in the validation circuit, the patent eliminates the need for complex multiple test patterns. The validation circuit uses a straightforward delay replication approach that is easier to operate and configure than conventional multi-pattern testing methods.
Solution Approach 2:
The validation circuit automatically configures itself to match the critical path characteristics through the delay circuit, which is designed to replicate the timing behavior of the original critical path. This self-configuration reduces the operational complexity and manual intervention required compared to conventional testing approaches.
3Device complexity
If conventional testing circuits are used, then simple circuit design is maintained, but critical paths that are infeasible for excitation remain unvalidated
Solution Approach 1:
The validation circuit acts as an intermediary that bridges the gap between simple circuit design and complete validation coverage. By using a delay circuit that replicates critical path timing characteristics, the validation circuit can test previously infeasible paths without adding significant complexity to the overall system.
Solution Approach 2:
The patent creates a validated copy of the critical path that can be excited and tested independently. This copy allows the system to validate even those critical paths that were previously infeasible to excite, while maintaining the simplicity of the original circuit design through the use of identical standard circuit components.
Data Source
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Figure 3A
AI summary
A validation circuit is placed in vicinity of a critical path for testing the critical path. The validation circuit receives test data from the control circuit for testing the critical path. The test data is indicative of a delay value that is associated with the critical path. The validation circuit generates multiple setup signals and an enable signal to facilitate the testing of the critical path based on the test data. The validation circuit generates a first test signal based on the enable signal, and a second test signal based on the first test signal and the setup signals. The second test signal is a delayed version of the first test signal. The validation circuit compares the first test signal and the second test signal. A mismatch between the first test signal and the second test signal indicates deviation from the delay value.