Cross-Channel ECC Merging for Memory RAS Without Lockstepping

The patent merges error correction capabilities across multiple memory channels by combining ECC locators from different channels. When a device failure is detected in one channel, the system merges the ECC locator from the failed channel with the ECC locator from another channel, allowing the combined ECC information to correct errors without requiring dedicated spare capacity in a single channel. This distributes the reliability function across channels rather than concentrating it in a reserved rank.

The patent implements a dynamic error correction approach where the system adapts its correction strategy based on the actual error patterns detected. Rather than continuously operating in a fixed lockstepping mode that consumes high power, the system dynamically selects between different correction methods (single channel correction, merged channel correction, or cross-channel merging) depending on the failure mode detected, thereby reducing power consumption while maintaining reliability.

The patent segments the error correction function into independent channel-level operations rather than requiring synchronized lockstepping across entire memory ranks. Each channel can be corrected independently or merged with another channel as needed, allowing parallel processing of multiple channels and maintaining higher bandwidth utilization while achieving the same reliability goals through distributed correction rather than centralized lockstepping.

The patent creates a universal error correction mechanism that can handle multiple failure modes through a single merged ECC framework. The same merged ECC locator structure serves multiple functions: it can correct single-device errors within a channel, double-device errors across channels, and adapt to different failure patterns without requiring separate correction schemes. This multi-functionality improves serviceability by providing a unified approach to handling various memory failures.