Error Correction/Detection Using Block Codes TRIZ Cases
- Memristive Dot-Product Engine With Redundant Columns for Error Correction
Redundant crossbar columns encode parity data to detect and correct memristive dot-product errors caused by noise, faults, and programming inaccuracy.
- Hierarchical Neural Network Coupling Using Error-Correcting Codes
An error-correcting code matrix predefines loose node couplings, cutting pre-learning time and computation in hierarchical classifiers.
- Storage Interface Timing Adjustment for Signal Integrity
Concurrent host and memory interface phase adjustment improves calibration accuracy, reduces errors, and strengthens storage signal integrity.
- Memristive Dot-Product Engine Using Redundant Crossbar Columns
Encoded redundant columns and syndrome lookup decoding correct memristive crossbar faults to keep dot-product outputs accurate and reliable.
- Multicast FEC Sub-Streams for Reliable Wireless Video Capacity
Receiver-driven FEC sub-stream subscriptions improve multicast video reliability under packet loss while limiting wireless bandwidth use.
- Embedded ECC in FPGA Configuration Memory Using Don't Care Bits
Don't care configuration bits are reused to store parity and error codes, enabling fast SEU detection and correction with low hardware overhead.
- Nonvolatile Memory Block Refresh Using Cross-Page Error Monitoring
Cross-page error checks during reads trigger block refresh before ECC limits are exceeded, protecting nonvolatile memory data integrity.
- Bus Width Conversion Parity Handling for Forwarded Error Detection
Precomputed parity and forwarded error encoding help bus width converters detect mismatches and preserve data integrity across width changes.
- Adaptive ECC Coverage in Memory Arrays for Variable Error Rates
Variable ECC coverage lets memory arrays match correction strength to local error rates, reducing unrecoverable errors without extra code storage.
- PLCP Header Encoding for Early Cyclic Prefix Detection
CP mode bits placed in the first PLCP header symbol let receivers set guard interval timing early, cutting latency and improving bandwidth use.
- Flash Memory Data Disordering With ECC for Secure Firmware Access
ECC encoding and data disordering disperse flash data, spare area, and parity codes to protect firmware transfer integrity.
- Collective Block Padding and Interleaving for Multicarrier Encoding
Padding grouped data blocks before or after interleaving cuts interleaver count and processing time in multicarrier encoding.
- Cross-Channel ECC Merging for Memory RAS Without Lockstepping
Merging ECC locators across memory channels corrects permanent device failures while preserving bandwidth and avoiding lockstepping capacity costs.
- Block-Request HTTP Streaming With FEC for Fast Channel Switching
Parallel HTTP block requests with erasure-coded media cut channel switching time while sustaining playback under changing bandwidth.
- SSD Data Positioning Across Dies and Pages to Reduce Bit Errors
Varying write positions across dies, erase blocks, and pages helps solid-state storage average raw bit errors and improve reliability.
- Cache ECC Wordline Failure Detection Across Multiple ECC Words
Multiple ECC words on one cache wordline are checked together to flag failing wordlines and reduce data mis-correction.
- NAND Flash Error Block Tracking After Data Relocation
An error block table preserves logical and physical address links, helping trace ECC error blocks after NAND flash data relocation.
- Erasure-Coded Disk Allocation Across Flexible Drive Pools
Dynamic placement of erasure-coded blocks across pooled drives and algorithms improves seek efficiency, fault tolerance, and recovery.
- Memory Bit Correction Beyond ECC Limits Using Multiple Read Voltages
When ECC cannot fix all memory errors, multiple read voltages reveal alternate bit values that enable successful correction and decoding.
- Dual-Read ECC Error Detection for Hidden Storage Media Faults
Comparing ECC and non-ECC reads exposes corrected storage errors, helping locate failing media before faults accumulate.
- ECC Flash Memory Readout Using Synchronized Parity Flags
Synchronized parity flags let ECC memory output corrected read data without extra pins or unnecessary write recovery delays.
- Variable-Length ECC in Memory Controllers for Critical Data
Critical write data receives longer ECC codes, improving error correction in rewritable non-volatile memory without extending all writes.