NAND Flash Error Block Tracking After Data Relocation

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Solution Overview

Problem

In storage devices with NAND type flash memory, identifying the physical block where an ECC error occurred is challenging when the error is copied to a different physical block, as the correlation between logical and physical addresses is overwritten, making it difficult to trace the original error source.

Innovation Solution

A storage device with a controller and error correcting circuit that generates an error block table to register logical and physical addresses, allowing identification of the physical block where the ECC error occurred, even after data has been copied to a new block.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data is copied from one physical block to another in a background process, then the data can be relocated to a new physical block, but the correlation between logical address and original physical block is overwritten, making it difficult to identify the physical block where the ECC error actually occurred

Engineering Contradiction:
Improvedata relocation capabilityVSAvoiderror location information
Core Design Contradiction:
Adaptability or versatilityVSLoss of information

Solution Approach 1:

The patent segments the address correlation information into two parts: the main mapping table that handles current logical-to-physical address mapping, and a separate error location record that preserves the original physical block information where ECC errors occurred. This segmentation allows data to be relocated while maintaining separate tracking of error locations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary error location record that acts as a mediator between the data relocation process and error identification requirements. This intermediary structure stores the original physical block information independently from the current address mapping, allowing both data relocation and error tracing to coexist without conflict.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the logical address and physical block correlation is updated after copying data to a new physical block, then the mapping remains current for future operations, but the original physical block information is lost, preventing accurate error investigation

Engineering Contradiction:
Improveaddress mapping maintenanceVSAvoiderror source identification accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent performs a preliminary action by recording the original physical block information in the error location record before the data relocation and address mapping update occurs. This preliminary recording ensures that the error source information is preserved even though the main address mapping is subsequently updated to reflect the new physical block location.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a traditional address mapping table is used to manage logical and physical addresses, then the mapping can be updated efficiently during background processes, but it cannot preserve historical information about where ECC errors originally occurred

Engineering Contradiction:
Improveaddress mapping update efficiencyVSAvoiderror occurrence location
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent adds another dimension to the address mapping system by introducing a separate error location record that exists parallel to the main mapping table. This additional dimension stores historical error location information without interfering with the efficiency of address mapping updates, allowing both functionalities to operate independently and simultaneously.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9043675B2Storage device
Publication Date: 2015.05.26 KIOXIA CORP
  • US9043675B2 patent drawing
  • US9043675B2 patent drawing
  • US9043675B2 patent drawing

AI summary

A nonvolatile memory is configured with blocks as deletion units, each block having several pages that are configured as write units. A controller for the nonvolatile memory includes an error correcting circuit, which detects and corrects an error in data read out of a page in one of the blocks of the nonvolatile memory, the page being referenced by a logical address. The controller also determines an error occurrence when the error cannot be corrected. An error block table is provided to store the logical address where the error occurred, and a physical address corresponding to the logical address.