ECC Flash Memory Readout Using Synchronized Parity Flags
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Solution Overview
Problem
Conventional nonvolatile semiconductor memories with ECC (Error-Correcting Code) functionality suffer from degraded random access performance due to the need for a write recovery time, even when no errors are detected, leading to inefficiencies in data retrieval and storage.
Innovation Solution
A nonvolatile semiconductor memory system with an ECC processing circuit that outputs error-corrected data and parity flags, allowing for synchronization of data and flags without additional input/output pins, enabling improved access performance by eliminating the need for write recovery time when no errors are present.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC processing is implemented in nonvolatile semiconductor memory, then data reliability is improved, but access speed deteriorates due to mandatory write recovery time
Solution Approach 1:
The patent implements dynamic write recovery time management where the memory controller adapts the write recovery time based on actual error conditions. When no errors are detected in read data, the system eliminates or reduces the write recovery time, allowing faster access. When errors are detected, the full write recovery time is applied to ensure proper error correction. This dynamic adjustment resolves the contradiction between maintaining reliability through ECC processing and achieving high access speed.
2Measurement precision
If error correction is always performed, then data accuracy is improved, but access time increases due to mandatory waiting period
Solution Approach 1:
The patent extracts the error correction operation from being a mandatory always-on process and makes it conditional. The system reads data and performs ECC checking, but only executes full error correction and applies write recovery time when errors are actually detected. When no errors are present, the system skips the correction wait period and proceeds directly to data output. This selective approach maintains data accuracy when needed while eliminating unnecessary time loss during error-free operations.
3Reliability
If write recovery time is enforced for all operations, then error correction reliability is improved, but productivity deteriorates due to unnecessary waiting
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors error detection results from ECC processing and uses this feedback to dynamically control write recovery time enforcement. The memory controller receives feedback about whether errors were detected in read operations and adjusts the write recovery time accordingly. This feedback-driven approach ensures error correction reliability is maintained when errors occur while maximizing productivity by eliminating unnecessary wait periods during error-free operations.
Data Source
AI summary
A nonvolatile semiconductor memory outputs the first parity flag corresponding to the error-corrected read data from the second input/output pin in synchronization with the error-corrected read data in the data buffer outputted from the first input/output pin.