SSD Data Positioning Across Dies and Pages to Reduce Bit Errors
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Solution Overview
Problem
Solid-state storage devices face bit error issues due to variations in reliability across memory cells, with some cells having higher raw bit error rates than others, leading to inconsistent data storage reliability.
Innovation Solution
The method involves varying data positioning across solid-state storage elements by determining different addresses using a deterministic pattern, storing and reading data in parallel across multiple positions to average the error rate, including different positions for dies, erase blocks, pages, and pages within the storage array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in fixed positions across solid-state storage elements, then storage simplicity is maintained, but bit error rate varies significantly across different memory cells
Solution Approach 1:
The patent applies local quality by varying data positioning strategies across different local regions of the storage array. Specifically, data is positioned differently across dies, erase blocks, and pages within pages based on their local error characteristics. This allows each local region to be optimized for its specific reliability profile, with data strategically placed in positions with lower error rates while maintaining overall system simplicity through automated management.
2Reliability
If data is stored in the same relative position across all solid-state storage elements, then access patterns are simplified, but error rates are inconsistent across the array
Solution Approach 1:
The patent segments the storage array into multiple hierarchical levels: dies, erase blocks, pages, and positions within pages. Data is distributed across these segments using varied positioning strategies at each level. This segmentation allows the system to achieve error rate consistency by treating different segments independently while maintaining ease of operation through automated management of the segmentation hierarchy.
Solution Approach 2:
The patent introduces multiple dimensions of variation in data positioning: across different dies, within different erase blocks, at different page levels (upper/lower pages), and at different positions within pages. This multi-dimensional approach allows the system to achieve consistent error rates by distributing data across many dimensions of the storage array while maintaining simplified access through automated address management.
3Reliability
If varied data positioning is implemented across all storage elements, then bit error rate is reduced, but address determination complexity increases
Solution Approach 1:
The patent implements periodic variation in data positioning by systematically cycling through different dies, erase blocks, page combinations, and positions within pages. This periodic pattern allows for deterministic address determination while achieving varied data positioning. The systematic cycling reduces raw bit error rates through diverse positioning while maintaining manageable address determination complexity through the regular, predictable nature of the periodic action.
Data Source
AI summary
Devices, apparatuses, systems, and methods are disclosed for bit error reduction through varied data positioning. A write request module is configured to receive data for storage in an array of solid-state storage elements. The solid-state storage elements are accessible in parallel. A write module is configured to store the data in parallel to the array of solid-state storage elements with varied data positions for the data relative to different solid-state storage elements of the array. A read module is configured to read the data in parallel from the array of solid-state storage elements.