Storage Interface Timing Adjustment for Signal Integrity
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Solution Overview
Problem
Non-volatile storage devices face issues with interface signal integrity due to poor calibration of timing signals, leading to errors and data loss, especially in high-frequency and large-memory systems, where signal attenuation and reflections cause bottlenecks that reduce device performance.
Innovation Solution
Implementing an interface timing adjustment engine that adjusts the phase of timing signals in both the memory interface and host interface concurrently, using memory access operations to improve calibration accuracy and account for worst-case scenarios, thereby enhancing signal integrity and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impedance matching is performed between host device and storage device, then signal attenuation and reflections are reduced, but device complexity increases due to additional calibration circuits
Solution Approach 1:
The patent combines the host interface calibration and memory interface calibration into a single unified adjustment process. The controller performs both calibrations concurrently using shared circuitry, eliminating the need for separate calibration circuits for each interface. This merging approach maintains signal integrity for both interfaces while reducing overall device complexity and resource utilization.
Solution Approach 2:
The calibration circuit is designed to perform multiple functions by sequentially calibrating both the host interface and memory interface using the same hardware resources. The circuit can operate in different calibration modes (host interface mode, memory interface mode) without requiring dedicated circuits for each function, thereby reducing device complexity while maintaining reliability.
2Measurement precision
If timing signal phase is adjusted to avoid bit transitions, then data sampling accuracy is improved, but adjustment process time increases
Solution Approach 1:
The patent performs timing signal phase adjustment as a preliminary action during the initialization sequence, before normal data operations begin. By completing the calibration process upfront using a message from the host device to initiate adjustment, the system establishes optimal sampling points in advance, ensuring high data sampling accuracy during subsequent operations without incurring time penalties during active data transfer.
Solution Approach 2:
The calibration process is designed to be performed continuously or periodically based on host device messages, ensuring that timing adjustments remain optimal without significantly impacting operational time. The system maintains calibrated state through continuous monitoring and periodic re-adjustment, balancing sampling accuracy with operational efficiency.
3Manufacturing precision
If interface calibration is performed separately for host interface and memory interface, then each interface can be optimized independently, but overall system performance is reduced due to sequential processing
Solution Approach 1:
The patent merges the calibration processes of the host interface and memory interface into a single concurrent operation. The controller receives a message from the host device to initiate adjustment and simultaneously performs both host interface calibration and memory interface calibration using shared circuitry. This approach maintains the precision of independent interface optimization while eliminating the sequential processing bottleneck, thereby improving overall system throughput.
4Measurement precision
If more calibration circuits are added to improve timing accuracy, then phase adjustment precision is improved, but resource utilization increases
Solution Approach 1:
The patent designs a universal calibration circuit that can perform phase adjustment for both the host interface and memory interface using the same hardware resources. The circuit is configured to operate in different modes (host interface calibration mode, memory interface calibration mode) sequentially or concurrently, eliminating the need for duplicate calibration circuits. This approach maintains high phase adjustment precision while minimizing circuit resource utilization.
Data Source
AI summary
A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.