Semiconductor Memory ECC Layout for Cross-Chip Error Recovery
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Solution Overview
Problem
NAND flash memory devices face increased random errors due to finer patterning processes, leading to data loss and burst failures, which existing error correction methods struggle to address effectively, especially in large data blocks and across multiple memory chips.
Innovation Solution
A semiconductor memory device is designed with multiple memory chips, each containing planes with first and second storage areas, utilizing error check and correction codes, including Reed-Solomon codes, to generate redundant data for error correction across pages and blocks, enhancing error correction capabilities and handling burst and random errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a powerful error correction capability is implemented using Reed-Solomon codes, then random error correction capability is improved, but the amount of error correction code increases
Solution Approach 1:
The patent divides the error correction scheme into two independent parts: BCH codes for random error correction at the page level, and Reed-Solomon codes for burst error correction at the block level. This segmentation allows each code to be optimized for its specific error type without requiring excessive redundancy for both error types simultaneously, thus improving random error correction capability while controlling the total amount of error correction code.
2Manufacturing precision
If finer patterning process is used to increase memory capacity, then manufacturing precision is improved, but burst failure probability increases
Solution Approach 1:
The patent introduces an intermediate error correction layer using BCH codes that operates at the page level before data is organized into blocks for Reed-Solomon correction. This intermediate layer acts as a mediator that handles random errors early in the correction process, preventing them from propagating and causing burst failures at the block level, thus mitigating the increased burst failure probability caused by finer patterning processes.
3Quantity of substance
If multiple memory chips are combined to increase storage capacity, then quantity of storage is improved, but data failure probability increases
Solution Approach 1:
The patent merges multiple memory chips into a unified storage system where data is distributed across chips but error correction is performed collectively at the block level using Reed-Solomon codes. By combining the error correction capability across multiple chips rather than treating each chip independently, the system achieves better overall reliability that scales with capacity, counteracting the increased data failure probability that would normally result from using multiple chips.
Data Source
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AI summary
A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.