Memory Loss Protection TRIZ Cases
- NAND Flash ECC Architecture for Random and Burst Error Recovery
Layered BCH, CRC, and Reed-Solomon coding across chips restores large NAND flash blocks despite random errors and burst failures.
- NAND Flash Memory Error Correction Across Chips and Planes
Combining BCH, CRC, and Reed-Solomon codes across chips and planes helps NAND flash recover random errors and burst failures without large ECC overhead.
- Stack Error Code Differencing for Fast Corruption Detection
Differential error codes track only used stack regions during interrupts and resumes, cutting overhead while detecting stack destruction.
- Memory Error Correction Circuit With Parallel Partial-Word Parity Check
Parallel partial-word parity checking and segmented error correction cut memory access delay as word length increases.
- Semiconductor Memory ECC Layout for Cross-Chip Error Recovery
Page-level BCH and cross-chip Reed-Solomon coding restore large memory blocks while limiting redundancy for random and burst errors.
- DRAM Retention-Time PUF for Unpredictable Cryptographic Keys
DRAM cell charge leakage creates bit-flip addresses that form a physically unclonable function and resist predictable key generation.
- Semiconductor Memory ECC Paging for Burst and Random Errors
Separate ECC pages combine Reed-Solomon and BCH coding to restore large NAND flash data blocks while limiting redundancy growth.
- SSD NAND Flash Parity Migration for Multi-Page Error Recovery
Valid sub-page data is moved to a new NAND region to rebuild parity, extending SSD recovery beyond single-page RAID errors.
- Flash Memory ECC with Selective Compression by Wear Level
Selective data compression in worn flash blocks preserves ECC size while improving error correction and data reliability over device aging.
- Semiconductor Memory ECC Layout for Random and Burst Errors
Layered BCH, CRC, and cross-chip Reed-Solomon coding corrects random and burst NAND flash errors without excessive ECC overhead.
- Hybrid ECC Switching for Worn Non-Volatile Memory Blocks
Switching between 1-bit and 2-bit ECC by block erase count preserves data integrity in worn memory while limiting power and overhead.