Semiconductor Memory ECC Paging for Burst and Random Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory devices face increased random errors due to finer patterning processes, leading to data loss and burst failures, especially in large data blocks, requiring enhanced error correction capabilities while maintaining efficient data storage.
Innovation Solution
A semiconductor memory device with multiple error correction mechanisms, including Reed-Solomon codes and BCH codes, is implemented to generate and record error check and correction codes across multiple memory chips, allowing for both burst and random error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction capability is enhanced to correct random errors, then data reliability is improved, but the amount of error correction code increases
Solution Approach 1:
The error correction code is segmented into two distinct types: burst error correction code (first error correction code) and random error correction code (second error correction code). This segmentation allows the system to address different error types with appropriately sized codes, preventing the need to use excessive code for all error types uniformly.
Solution Approach 2:
Different error correction capabilities are applied to different parts of the data structure. The burst error correction code handles large-scale block errors, while the random error correction code handles individual bit errors. This local quality approach optimizes the overall code amount by matching correction strength to error type.
2Quantity of substance
If finer patterning process is used to increase memory capacity, then storage density is improved, but the number of random errors and burst failures increases
Solution Approach 1:
The error correction mechanism is segmented into two independent code systems that work together. The first error correction code handles burst failures that become more common with finer patterning, while the second error correction code handles random errors. This dual-segmented approach maintains reliability despite increased error rates from advanced patterning processes.
Solution Approach 2:
The patent applies error correction codes during the data writing process as a preventive measure. By beforehand cushioning the data with redundant correction codes, the system prepares for potential burst failures and random errors that may occur during storage, especially those induced by finer patterning processes.
3Reliability
If multiple error correction codes are implemented to handle both burst and random errors, then comprehensive error protection is improved, but device complexity increases
Solution Approach 1:
The error correction function is segmented into two distinct code generation and processing units. The first error correction code handles burst errors, and the second error correction code handles random errors. This segmentation allows each unit to be optimized independently while working together to provide comprehensive protection.
Solution Approach 2:
The error correction system is designed with multi-functionality where the same memory structure and basic correction logic handle both burst and random errors through different code types. This universality reduces device complexity by avoiding the need for entirely separate correction mechanisms for each error type.
Data Source
AI summary
A semiconductor memory device including a memory chip; a first encoder/decoder section configured to obtain a first error check code based on original data and a first error correction code based on the original data and the first error check code, the first error check code and the first error correction code being recorded on a first page of the memory chip; and a second encoder/decoder section configured to obtain a second error check code and a third error correction code based on the original data, the second error check code being obtained based on the third error correction code, the second error check code and the third error correction code being recorded on a second page of the memory chip.