Semiconductor Device Memory Access with Separate ECC Address Paths
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Solution Overview
Problem
Existing semiconductor systems face reliability issues due to bit errors occurring in common address signals for data and syndrome-code access, leading to undetected errors in ECC checking.
Innovation Solution
The semiconductor device employs separate paths for memory access between the CPU and memory controllers, ensuring that data and error detection codes are stored and retrieved from different memory locations, allowing for independent error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common address signal path is used for data access and syndrome-code access, then circuit complexity is reduced, but reliability deteriorates due to undetected bit errors in common address signals
Solution Approach 1:
The patent divides the address signal path into two separate independent paths: one for data access and another for syndrome-code access. This segmentation ensures that bit errors in common address signals cannot affect both data and syndrome code simultaneously, thereby resolving the reliability issue while maintaining reasonable circuit complexity through modular design.
Solution Approach 2:
The patent introduces an address conversion circuit as an intermediary component that converts the original address signal into separate address signals for data access and syndrome-code access. This intermediary ensures that even if the original address signal contains errors, the converted addresses will correctly point to corresponding data and syndrome code locations, preventing undetected errors.
2Reliability
If separate paths are used for data access and syndrome-code access, then reliability is improved by preventing undetected errors, but device complexity increases
Solution Approach 1:
The address conversion circuit is designed to handle multiple functions: it converts addresses for both data access and syndrome-code access, and can adapt to different memory configurations. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving separate access paths.
Solution Approach 2:
The patent changes the address parameter by applying conversion logic that transforms the original address into modified addresses suitable for separate data and syndrome code access. This parameter transformation allows the system to use the same physical memory resources with different address mappings, achieving reliability improvement without proportionally increasing hardware complexity.
Data Source
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AI summary
A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.