Memory Error Correction Circuit With Parallel Partial-Word Parity Check
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Solution Overview
Problem
In memory systems, the increased word length leads to delays in error correction processing due to the need for serial arrangement of multiple gates and increased wiring load, which impedes access speed and processor speedup.
Innovation Solution
A data processing circuit that divides main body data into partial words and generates error correction additional bits as parity bits for each partial word, allowing parallel error correction and parity check, thereby reducing circuit delay and improving access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the data length per word is increased to improve memory capacity, then the storage capacity is improved, but the delay for error correction processing is increased due to serial arrangement of gates and increased wiring load
Solution Approach 1:
The patent divides the word data into multiple sub-words (e.g., four 32-bit sub-words from a 128-bit word) and processes each sub-word independently through separate error correction circuits. This segmentation allows parallel processing of error correction for each sub-word, significantly reducing the overall processing delay compared to serial processing of the entire word data.
2Reliability
If the number of gates is increased to handle longer data words, then the error correction capability is improved, but the circuit complexity and wiring load are increased
Solution Approach 1:
The error correction circuit is segmented into multiple independent sub-circuits, each handling a portion of the word data. This reduces the complexity of individual circuits while maintaining overall error correction capability through parallel operation.
Solution Approach 2:
Multiple sub-word error correction circuits are merged into a unified error correction system that processes the entire word data. The syndromes from multiple sub-words are combined to determine the overall error status, achieving comprehensive error correction without requiring a single complex circuit.
Data Source
AI summary
A data processing circuit includes an error processing circuit and a memory. Word data is configured by main body data to be divided into a plurality of partial words and redundant data. The redundant data is configured by error correction additional bits generated from the main body data on the basis of a predetermined error correction algorithm and the error correction additional bits include a plurality of parity bits corresponding to the partial words. The error processing circuit includes error correction circuit and parity check circuit into which the word data is input in parallel. The error correction circuit decides an error type by using the redundant data and corrects a correctable error. The parity check circuit performs a parity check on the basis of access-requested partial word and the corresponding parity bit.