Semiconductor Memory ECC Layout for Random and Burst Errors
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Solution Overview
Problem
NAND flash memory devices face increased random errors due to finer patterning processes, leading to data discharge issues and burst failures, which require powerful error correction capabilities but result in increased error correction code sizes, and as semiconductor memory devices grow in capacity, the likelihood of failures increases dramatically.
Innovation Solution
A semiconductor memory device is designed with multiple error check and correction code generations, including Reed-Solomon codes, to efficiently correct errors across memory chips and pages, utilizing cyclic redundancy check (CRC) and Bose-Chaudhuri-Hocquenghem (BCH) codes for error detection and correction, and employing error correction codes to restore large data block failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If powerful error correction capability is implemented to correct random errors from finer patterning, then data retention is improved, but error correction code size increases
Solution Approach 1:
The patent divides error correction into multiple independent code systems: BCH codes for random errors, RS codes for burst errors, and CRC for error detection. Each code type handles specific error patterns, allowing efficient error correction without requiring a single large code that would increase storage overhead.
Solution Approach 2:
The patent employs a composite error correction approach by combining multiple error correction code types (BCH, RS, CRC) into a unified system. This composite strategy leverages the strengths of each code type to achieve powerful error correction capability while maintaining reasonable code size through specialized division of labor.
2Reliability
If multiple error correction code types are used to handle both random and burst errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction system into distinct functional modules: BCH decoding for random errors, RS decoding for burst errors, and CRC checking for error detection. Each module is independently optimized for its specific function, which manages complexity by avoiding the need for a single monolithic complex system.
Solution Approach 2:
The patent implements dynamic error correction processing that adapts to the type of errors detected. The system can selectively activate different decoding paths (BCH, RS, or both) based on error patterns, which reduces the operational complexity compared to always using the most powerful correction method.
3Duration of action of stationary object
If error correction codes are added to correct data discharge over time, then data retention is improved, but storage space for codes increases
Solution Approach 1:
The patent segments error correction codes into page-level BCH codes and block-level RS codes. This segmentation allows efficient use of storage space by applying different code densities to different data granularities, optimizing the balance between data retention capability and storage overhead.
Data Source
AI summary
A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.