MLC Flash Storage Using Audit Bits for SLC-Like Reliability

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Solution Overview

Problem

Multi-level cell (MLC) solid-state storage devices face reduced longevity and increased error rates due to the storage of multiple bits in a single memory cell, which compromises data integrity and device lifespan, especially under high temperature conditions or power loss.

Innovation Solution

Implementing a method that uses multi-level memory cells with audit bits to validate data bits by reading them separately and flipping suspect data bits based on audit bit mismatches, allowing the storage device to operate as single-level cell (SLC) storage when reliability thresholds are met, thereby extending device lifespan and improving data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple bits are stored in a single memory cell to increase capacity, then storage capacity increases, but device longevity and reliability decrease

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice longevity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the multi-level cell storage into separate functional components: data bits are stored in one location while audit bits are stored in another location within the same memory cell. This segmentation allows independent verification of data integrity through separate read operations, resolving the contradiction by maintaining high capacity utilization while improving reliability through distributed storage and verification mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces audit bits as an intermediary element that mediates between the stored data and the verification process. These audit bits serve as a checkpoint mechanism that can be read separately to determine whether data bits have been corrupted, allowing the system to detect and handle errors without requiring complete rewriting of all data, thus extending device longevity while maintaining high storage capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If MLC storage is used to reduce cost per bit, then manufacturing cost decreases, but error rates increase under high temperature or extended storage conditions

Engineering Contradiction:
Improvecost per bitVSAvoiddata integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by storing audit bits alongside data bits at the time of writing, creating a verification mechanism in advance. This allows the system to proactively detect data corruption before it affects operational reliability, enabling early error detection and correction without requiring more expensive hardware, thus maintaining cost-effectiveness while improving data integrity under stressful conditions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the audit bit verification mechanism, where the state of audit bits provides information about data integrity. When audit bits indicate corruption, the system can trigger error correction procedures or data recovery protocols, creating a closed-loop feedback system that maintains reliability without increasing manufacturing complexity or cost.

Inventive Principle:
Principle #23Feedback

3Reliability

If audit bits are read in separate operations to verify data validity, then data integrity improves, but access time increases

Engineering Contradiction:
Improvedata validityVSAvoidaccess time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing audit bit verification only when necessary - such as when errors are detected or under specific system conditions - rather than continuously verifying every read operation. This selective verification approach maintains data integrity through targeted checks while minimizing the impact on overall access time, resolving the contradiction between reliability and speed.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20100235715A1Apparatus, system, and method for using multi-level cell solid-state storage as single-level cell solid-state storage
Publication Date: 2010.09.16 SANDISK TECHNOLOGIES LLC
  • US20100235715A1 patent drawing
  • US20100235715A1 patent drawing
  • US20100235715A1 patent drawing

AI summary

An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.