NAND Flash Memory Error Correction Across Chips and Planes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory devices face increased random errors due to finer patterning processes, leading to data loss and burst failures, especially as semiconductor memory capacities grow, requiring enhanced error correction capabilities without significantly increasing error correction code sizes.
Innovation Solution
A semiconductor memory device with multiple error correction mechanisms, including Reed-Solomon codes and BCH codes, is implemented to generate redundant codes for data blocks, allowing for both burst and random error correction across memory chips, enhancing overall error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction capability is enhanced to correct random errors, then data reliability is improved, but error correction code size increases
Solution Approach 1:
The error correction code is divided into two distinct types: burst error correction code (BECC) and random error correction code (RECC). This segmentation allows each code type to be optimized for its specific error correction function, preventing the need to increase overall code size uniformly for both error types. The BECC handles burst errors while RECC handles random errors, achieving comprehensive error correction with minimal total code overhead.
Solution Approach 2:
The patent applies partial action by using different error correction codes for different error types rather than using a single comprehensive code. The BECC is designed specifically for burst errors with appropriate code length, and RECC is designed specifically for random errors. This partial specialization avoids the excessive code size that would result from using a single powerful code capable of correcting both error types.
2Quantity of substance
If finer patterning process is used to increase memory capacity, then storage density is improved, but random errors and burst failures increase
Solution Approach 1:
The error correction mechanism is segmented into two independent code systems: BECC for burst failures and RECC for random errors. This segmentation allows the system to address both types of errors that arise from finer patterning processes without requiring a single overly complex error correction system, thereby maintaining data reliability while enabling high-density storage.
Solution Approach 2:
The patent changes the parameters of error correction by selecting different code types and code lengths for different error scenarios. The BECC uses parameters optimized for burst error correction, while RECC uses parameters optimized for random error correction. This parameter differentiation enables effective error correction in high-density memory where both error types are prevalent.
3Reliability
If multiple error correction codes are implemented, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The error correction function is segmented into two independent but complementary code systems. The BECC and RECC operate independently for their respective error types, which simplifies the overall system architecture compared to using a single complex universal error correction code. Each code can be implemented and managed separately, reducing the complexity burden.
Solution Approach 2:
The dual-code system provides universal error correction capability by handling both burst errors and random errors within a unified error correction framework. This multi-functionality is achieved not by making one complex code do everything, but by coordinating two simpler specialized codes, thereby reducing overall device complexity while maintaining comprehensive error correction capability.
Data Source
AI summary
A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.