NAND Flash ECC Architecture for Random and Burst Error Recovery
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Solution Overview
Problem
NAND flash memory chips face challenges with increased discharge of electric charges leading to random errors and burst failures due to finer patterning processes, especially in large data blocks, requiring stronger error correction capabilities that increase the amount of error correction codes and affecting peripheral circuits.
Innovation Solution
Implementing a semiconductor memory device with a configuration that includes error correction codes using Reed-Solomon codes, along with cyclic redundancy check and Bose-Chaudhuri-Hocquenghem codes, to enhance error correction capabilities across memory chips and blocks, allowing for efficient error correction and restoration of large data blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction capability is strengthened to correct random errors from charge discharge, then data reliability is improved, but the amount of error correction code increases
Solution Approach 1:
The error correction system is segmented into multiple independent coding schemes: BCH codes for random errors, RS codes for burst errors, and CRC for error detection. Each code handles specific error types, allowing the system to achieve comprehensive error correction without requiring a single large-volume code, thus improving reliability while controlling code amount.
Solution Approach 2:
The patent employs different error correction codes with varying parameters for different error scenarios. BCH codes with specific polynomial orders handle random errors, while RS codes with different symbol counts handle burst errors. This parameter-based approach allows optimization of code amount for each error type, resolving the contradiction between reliability and code quantity.
2Manufacturing precision
If finer patterning process is used to increase memory capacity, then manufacturing precision is improved, but burst failure rate increases due to peripheral circuit failures
Solution Approach 1:
The data storage is segmented into multiple blocks with independent error correction capabilities. Each block contains data pages and spare pages with embedded RS codes. This segmentation ensures that a burst failure affecting one block does not propagate to other blocks, maintaining reliability despite finer patterning that increases overall device complexity and potential failure points.
Solution Approach 2:
RS codes act as an intermediary mechanism between the physical memory blocks and the logical data storage. These codes provide a buffer that can correct burst errors caused by peripheral circuit failures in finely patterned devices, mediating between the improved manufacturing precision and the increased susceptibility to burst failures.
3Reliability
If multiple error correction codes are implemented to handle both random and burst errors, then comprehensive error correction is achieved, but device complexity increases
Solution Approach 1:
The error correction system is divided into specialized modules: BCH decoding for random errors, RS decoding for burst errors, and CRC checking for error detection. Each module handles a specific error type independently, allowing comprehensive error correction while managing complexity through functional segmentation rather than a monolithic complex system.
Solution Approach 2:
The patent implements a multi-functional error correction framework where RS codes in spare pages can serve dual purposes: correcting burst errors in data pages and providing additional redundancy for random errors. This universality allows multiple error correction functions to be achieved without proportionally increasing device complexity, as the same code structure serves multiple protective roles.
Data Source
AI summary
A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.