SSD NAND Flash Parity Migration for Multi-Page Error Recovery
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Solution Overview
Problem
In Solid State Drives (SSDs) using NAND flash memory, data errors across two or more pages cannot be recovered using traditional RAID techniques, limiting data recovery capabilities.
Innovation Solution
A method for controlling a nonvolatile memory device that reads sub stripes with multiple sub pages, performs RAID recovery on single erroneous sub pages, sets recovery fail flags for multiple erroneous sub pages, and migrates valid sub page data to a different memory region to generate parity data, enabling data recovery even when errors occur in multiple pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional RAID techniques are used for data recovery in NAND flash memory, then data recovery is possible for single page errors, but data recovery fails when errors occur in two or more pages
Solution Approach 1:
The patent divides the memory space into multiple regions (first memory region and second memory region) and implements RAID striping at the sub-page level across these regions. By segmenting data into multiple sub-pages distributed across different memory regions, the system enables RAID recovery capability to extend beyond single-page errors to handle multi-page errors effectively.
Solution Approach 2:
The patent introduces a new dimension to RAID implementation by creating a second memory region specifically for storing migrated valid data and generating parity data. This dimensional expansion allows the system to perform RAID recovery operations across multiple pages by leveraging the spatial distribution of data across different memory regions, overcoming the limitation of traditional single-region RAID.
2Reliability
If valid data is migrated to a different memory region to generate parity data, then data recovery capability improves for multiple erroneous pages, but memory operation complexity increases
Solution Approach 1:
The patent performs preliminary migration of valid data from the first memory region to the second memory region before errors occur. This preliminary action establishes the parity data structure in advance, enabling rapid RAID recovery operations when errors are detected without requiring complex real-time data manipulation during recovery operations.
Solution Approach 2:
The second memory region acts as an intermediary structure that stores migrated valid data and facilitates parity generation. This intermediary region simplifies the recovery process by providing a dedicated space for RAID operations, separating the storage function from the recovery function and reducing overall system complexity.
3Productivity
If RAID striping is implemented on a page-by-page basis, then input and output operations are balanced, but data cannot be recovered when errors occur in two or more pages
Solution Approach 1:
The patent segments data into sub-pages and distributes them across multiple memory regions with RAID striping, maintaining the balanced I/O operations benefit while extending error recovery capability to multiple pages through the distributed sub-page structure and parity generation in the second memory region.
Solution Approach 2:
The patent creates a universal RAID structure that handles both single-page and multi-page errors through the same mechanism. The second memory region serves multiple functions: storing migrated valid data, generating parity data, and enabling recovery operations, making the RAID system universally applicable to various error scenarios while maintaining I/O balance.
Data Source
AI summary
A method for controlling a nonvolatile memory device includes reading a sub stripe including a plurality of sub pages stored in a first region, writing data stored in valid sub pages of the sub stripe to a second region different from the first region, and generating parity data using the data written to the second region and constituting a new sub stripe.