Cross Clock Domain Transition Scan Coverage Synchronization
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Solution Overview
Problem
Conventional scan testing methods fail to effectively synchronize capture clocks across multiple clock domains, leading to gaps in transition scan coverage and missed data transfers between clock domains, which can result in false security regarding critical timing paths.
Innovation Solution
The synchronization of capture clocks is achieved by generating clock signals with specific active edge timing relationships, where each faster clock's active edge occurs one clock period before the active edge of each slower clock, ensuring that transitions are captured at speed across all clock domains through on-chip clock control circuits and controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan testing methods are used without clock synchronization, then the testing process is simpler and faster to implement, but transition scan coverage is insufficient and data transfers between clock domains are missed
Solution Approach 1:
The patent applies preliminary action by synchronizing capture clocks across multiple clock domains before the actual scan testing begins. The method pre-aligns the active edges of capture clocks with respect to scan enable signal deassertion, ensuring that all clock domains are properly synchronized prior to capturing test data. This preliminary synchronization prevents missed data transfers and improves transition scan coverage without adding complexity during the actual testing operation.
Solution Approach 2:
The patent uses the scan enable signal as an intermediary to coordinate and synchronize multiple capture clocks across different clock domains. By referencing the deassertion time of the scan enable signal, the method creates a common reference point that mediates the timing relationships between fast and slow clock domains, enabling reliable cross-clock-domain testing without direct complex inter-clock synchronization circuits.
2Measurement precision
If capture clocks are not synchronized, then the testing implementation is easier, but critical timing path failures are not detected leading to false security
Solution Approach 1:
The patent replaces complex mechanical-style clock synchronization circuits with a signal-timing-based approach. Instead of using dedicated synchronization hardware or complex inter-clock routing, the method uses the temporal relationship between the scan enable signal deassertion and capture clock active edges to achieve synchronization. This substitution simplifies the testing implementation while maintaining high precision in detecting critical timing path failures.
3Reliability
If multiple clock domains are tested without synchronization, then the test setup is simpler, but transition coverage gaps occur reducing test effectiveness
Solution Approach 1:
The patent applies universality by making the capture clocks across different clock domains subordinate to a common reference event (scan enable deassertion). This multi-functional approach allows the same synchronization mechanism to work across all clock domains regardless of their individual frequencies or functions, eliminating transition coverage gaps while avoiding the need for domain-specific complex control circuits for each clock pair.
Data Source
AI summary
In order to increase test coverage of integrated circuits with multiple clock domains, during a capture portion of a scan test, the functional clock signals, associated with a respective one of the clock domains are synchronized to ensure back and forth capture between the faster and slower clock domain. Each of the plurality of clock signals is generated such that an active edge of each faster clock signal occurs one clock period of the faster clock signal before an active edge of each slower clock signal.