Cross FET SRAM Cell Layout Using 3D GAA and Single-Via Routing
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Solution Overview
Problem
Modern semiconductor manufacturing faces challenges in designing memory bit cells due to issues like capacitive coupling, electro migration, short channel effects, and space constraints, which affect the placement and routing of components on semiconductor chips, leading to delays and inefficiencies in chip design and production.
Innovation Solution
The use of vertically stacked gate all-around (GAA) transistors with orthogonal orientations between top and bottom transistors, known as Cross FETs, reduces planar area consumption, increases performance, and minimizes power consumption and signal congestion by employing a single via layer for connections, thereby improving the layout efficiency of memory bit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar transistor layouts are used in memory bit cells, then routing and connection are simpler, but planar area consumption increases and device performance decreases
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor layouts to vertically stacked 3D transistor configurations. Multiple transistor layers are stacked above each other, utilizing the vertical dimension to reduce planar footprint while maintaining electrical connectivity through via connections between layers.
Solution Approach 2:
The patent implements nested transistor structures where smaller transistors are positioned within or adjacent to larger transistors in a hierarchical arrangement. This nesting allows multiple devices to share space efficiently, reducing overall planar area consumption while maintaining functional independence.
2Productivity
If more components are placed on the same die to increase functionality, then chip performance improves, but space constraints and interference with other components increase
Solution Approach 1:
By stacking transistors vertically in multiple layers, the patent enables more memory bit cells to be packed into the same die area. The vertical stacking multiplies the effective device density without increasing the horizontal die footprint, allowing higher functionality within constrained area.
Solution Approach 2:
The patent combines multiple transistor functions into integrated vertical stacks where shared structures (such as common source/drain regions or gate electrodes) serve multiple devices simultaneously. This merging reduces redundant structures and maximizes component density on the die.
3Area of moving object
If vertically stacked transistors are used to reduce planar area, then area efficiency improves, but manufacturing complexity and processing difficulty increase
Solution Approach 1:
The patent divides the vertically stacked transistor structure into discrete manufacturable layers, with each layer formed through separate processing steps. This segmentation allows standard semiconductor fabrication techniques to be applied sequentially to build the complex 3D structure, making manufacturing more manageable despite the increased complexity.
Data Source
AI summary
A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.