Cross-ISA Instruction Mapping for Low-Overhead Program Execution

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing techniques fail to provide a method for processors to execute instructions from a different instruction set effectively, particularly when non-common instructions are encountered, leading to inefficiencies and overhead due to unnecessary determination of replacement needs.

Innovation Solution

A program acquires correspondence information associating non-common instructions with common instructions executable by both processors, allowing the first processor to execute the corresponding common instructions upon detection of non-common instructions, thereby reducing overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a processor simulator is used to execute instructions from a different instruction set, then the processor can execute programs with non-common instructions, but the execution speed decreases and overhead increases due to determination of replacement needs

Engineering Contradiction:

Improveability to execute different instruction setsVSAvoidexecution speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent pre-generates correspondence information mapping non-common instructions to common instructions before execution. This preliminary action allows the processor to directly execute common instructions without runtime determination overhead, resolving the contradiction between adaptability and execution speed by preparing replacement mappings in advance

Inventive Principle:

Principle #10Preliminary action

2Reliability

If instruction replacement determination is performed for each non-common instruction, then accurate execution is ensured, but overhead increases and performance decreases

Engineering Contradiction:

Improveexecution accuracyVSAvoiddetermination overhead

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The correspondence information between non-common and common instructions is generated and stored in advance in a table or data structure. This eliminates the need for runtime determination, ensuring execution accuracy through pre-validated mappings while removing the time loss associated with real-time decision-making

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent creates a copy of the instruction execution path by mapping non-common instructions to equivalent common instructions through pre-generated correspondence information. This copying approach ensures accurate execution semantics are preserved while avoiding the overhead of real-time translation decisions

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12468533B2Instruction execution control apparatus and method using correspondence information between different processor instruction sets

Publication Date: 2025.11.11 RENESAS ELECTRONICS CORP

AI summary

An instruction execution control apparatus is configured to acquire correspondence information. The correspondence information associates a non-common instruction with a common instruction. The non-common instruction is an instruction not executable by a first processor but executable by a second processor. The common instruction is an instruction executable by both the first processor and the second processor. The instruction execution control apparatus is configured to use the correspondence information to specify the common instruction corresponding to the non-common instruction in response to the detection of the non-common instruction in the first processor. The instruction execution control apparatus causes the first processor to execute the specified common instruction.