Runtime Instruction Translation TRIZ Cases
- Multi-Core SWC Communication Buffer Allocation by Execution Cycle
Execution-cycle-based buffer placement cuts cache inefficiency and memory access latency in multi-core SWC communication.
- GPU Combined Instructions with Dual Data Pipes for Shader Bottlenecks
A compiler combines dependent GPU instructions across main and bypass pipes to ease CR bandwidth limits and improve shader SP utilization.
- GPU Convolution Hardware With Parallel Matrix Multiply Scheduling
Dedicated GPU multiply-accumulate hardware and thread scheduling speed convolution and matrix processing without relying only on fixed-function units.
- Remote Memory Access Scheduling to Reduce Processor Stalls
Non-blocking remote memory access with background instruction execution cuts processor stall time while preserving program correctness.
- Cross-ISA Instruction Mapping for Low-Overhead Program Execution
Prebuilt mappings let a first processor replace non-common instructions with shared ones, cutting runtime translation overhead.
- Scratchpad Memory Instruction Scheduling for AI Processor Throughput
Hazard detection lets AI processors run non-memory instructions during memory cycles while preserving memory order and correctness.
- Segmented Branch Target Buffers by Branch Type to Reduce Front-End Stalls
High code-footprint workloads cause BTB misses, front-end stalls, and re-steering; branch-type segmentation targets each branch class separately.
- Document Macro Conversion for Network Storage Compatibility
A macro conversion engine translates incompatible document macros before storage, preserving function while improving access and reducing latency.
- General-Purpose GPU SIMT Architecture for Machine Learning Operations
This case uses programmable GPU units and SIMT execution to expand beyond fixed graphics processing for machine learning workloads.
- Register Renaming Cache Replay for Lower RAT Power and Complexity
This case replays learned register mappings for instruction traces, easing RAT timing, allocation-width complexity, and power hotspots.
- Macro-Service Generation via Graph-Based Code Segmentation
Converting analytic source code into a graph representation enables automated generation of reusable macro-services, reducing manual coding effort and errors.
- Latency-Tolerant Microprocessor Queue Architecture
Segmenting instructions into distinct load and store queues allows parallel execution of independent operations, reducing memory access stall time.
- Chaining Exposed-Pipeline Processing Elements
Segmenting instructions and issuing sub-instructions at offset times reduces memory access latency while managing system complexity.
- Management Protocol Adapter for Server System Interoperability
A management protocol adapter translates commands between IPMI and Redfish standards to enable seamless communication across heterogeneous server systems.
- Instance Instrumentation for Tainted Data Tracking
Instanced instrumentation replaces only functions receiving untrusted input with instrumented versions that mark outputs as tainted.