GPU Combined Instructions with Dual Data Pipes for Shader Bottlenecks
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Solution Overview
Problem
Conventional GPU architectures face performance bottlenecks due to data dependencies among instructions, leading to inefficient use of Common Register (CR) bandwidth and wasted SP capacity, particularly in shader operations.
Innovation Solution
Introduce a novel GPU architecture with two data paths: a main-pipe for Algorithm, Compare, Logic, and Selection operations, and a bypass-pipe for data or constant reading and passing, allowing for combined instructions to be executed in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple instructions are executed using multiple data pipes in parallel, then processing speed is improved, but instruction complexity and compilation difficulty increase
Solution Approach 1:
The patent segments instructions into different types (calculation, comparison, logic, selection, branching, LD/ST, SMP, and complicated mathematics operations) and assigns them to different data pipes based on their specific requirements. This segmentation allows each data pipe to be optimized for its designated instruction type, improving parallel processing speed while maintaining manageable instruction complexity through systematic classification.
Solution Approach 2:
The patent introduces a compiler as an intermediary that automatically analyzes data dependencies between instructions and combines compatible instructions into combined instructions. This intermediary handles the complexity of parallel execution planning, allowing multiple instructions to be executed in parallel through the combined instruction mechanism without requiring manual intervention to manage the complexity.
2Productivity
If instructions are combined based on data dependencies, then execution efficiency is improved, but compilation complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the compiler automatically performs dependency analysis and instruction combination without external intervention. The system analyzes data dependencies between instructions, identifies compatible instruction pairs, and combines them into unified combined instructions that can be executed efficiently in parallel, thereby improving execution efficiency while managing compilation complexity through automation.
Solution Approach 2:
The patent changes the parameter of instruction representation by combining multiple instructions into a single combined instruction structure. This parameter change allows the system to represent complex parallel execution plans in a simplified form that maintains execution efficiency while reducing the apparent compilation complexity, as the combined instructions encapsulate the dependency relationships internally.
3Device complexity
If different data types are processed using the same data pipe, then device simplicity is maintained, but processing precision may be compromised
Solution Approach 1:
The patent applies local quality by assigning specific data types to specific data pipes based on their processing requirements. Different data pipes are optimized for different data types (e.g., floating-point operations in one pipe, integer operations in another), ensuring that each data type receives the appropriate processing precision while maintaining overall device simplicity through a systematic division of labor rather than requiring a single complex processing unit.
Data Source
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AI summary
A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).