Multi-Core SWC Communication Buffer Allocation by Execution Cycle
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Solution Overview
Problem
In multi-core systems, existing methods for communicating between software components (SWCs) degrade cache memory efficiency and reduce operation speed due to the lack of consideration for execution cycles when using cache memory as a data buffer.
Innovation Solution
A multi-core system determines a memory to operate as a data buffer based on the execution cycle of each SWC, optimizing memory access latency by allocating the data buffer in the core with the shorter execution cycle, thereby improving application operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used as a data buffer without considering execution cycle, then communication between SWCs is enabled, but cache memory efficiency is degraded and operation speed is reduced
Solution Approach 1:
The patent applies dynamics by making the data buffer allocation adaptive rather than static. The system dynamically determines which core's memory to use as the data buffer based on real-time execution cycle comparisons. When the first SWC's execution cycle is shorter, its core's memory is selected; otherwise, the second core's memory is selected. This dynamic adaptation optimizes both cache memory efficiency and operation speed by matching buffer allocation to actual execution characteristics.
Solution Approach 2:
The patent changes the parameter of memory buffer allocation from a fixed configuration to a variable decision based on execution cycle parameters. By comparing execution cycle durations and selecting the appropriate memory buffer accordingly, the system optimizes access patterns and reduces unnecessary cache operations, thereby improving both speed and energy efficiency.
2Productivity
If memory access latency is not optimized, then SWC communication is simplified, but application operation speed is reduced
Solution Approach 1:
The patent applies preliminary action by pre-determining the optimal data buffer location before SWC communication occurs. The system compares execution cycles and selects the appropriate memory buffer in advance, ensuring that data is stored in the memory with the most favorable access characteristics for the given execution pattern. This preliminary optimization reduces memory access latency during actual communication operations.
3Reliability
If data buffer is allocated without considering execution cycle, then system complexity is reduced, but memory access efficiency is degraded
Solution Approach 1:
The patent applies self-service by enabling the system to automatically determine the optimal data buffer allocation without external intervention. The multi-core system autonomously compares execution cycles of SWCs and selects the appropriate memory buffer based on this comparison, eliminating the need for complex external buffer management mechanisms while improving memory access efficiency.
Data Source
AI summary
A multi-core system for providing a communication function between software components (SWCs) and a method therefor are provided. The method may include: determining a memory operating as a data buffer, based on an execution cycle of each of the SWCs, when communicating between an SWC executed by a first core and at least one SWC executed by a second core; writing, by the SWC executed by the first core, data in the data buffer; and reading, by the at least one SWC executed by the second core, the data from the data buffer.