GPU Convolution Hardware With Parallel Matrix Multiply Scheduling
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Solution Overview
Problem
Current graphics processing units (GPUs) face challenges in efficiently performing a wide variety of operations due to the transition from fixed function computational units to programmable architectures, necessitating improved parallel processing techniques to enhance performance.
Innovation Solution
Implementing a graphics processing unit (GPU) with dedicated circuitry for efficient processing of commands and instructions, including a parallel processing unit with a scheduler to distribute workloads across processing clusters, and utilizing a unified memory architecture for seamless data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed function computational units are replaced with programmable architectures to support a wider variety of operations, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a unified processing cluster architecture where the same programmable processing elements can execute multiple types of operations including vertex processing, fragment processing, and compute operations. This universal design allows a single processor to handle diverse workloads without requiring separate fixed-function units for each operation type, thereby maintaining adaptability while controlling complexity through architectural unification
2Productivity
If parallel processing techniques are implemented to increase performance, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent divides the processing architecture into multiple independent processing clusters, each capable of executing parallel operations. Within each cluster, processing elements are segmented into specialized units for different operation types (vertex, fragment, compute), allowing fine-grained parallelism while maintaining manageable complexity through modular organization. This segmentation enables high productivity through parallel execution without requiring a monolithic complex architecture
Solution Approach 2:
The patent implements parallel processing by adding temporal and spatial dimensions to the architecture - multiple processing clusters operate simultaneously in space, while pipelining techniques enable multiple operation stages to progress concurrently through time. This dimensional approach to parallelism achieves high productivity without proportionally increasing structural complexity, as the parallelism is achieved through time-multiplexed resource sharing and staged processing
3Productivity
If pipelining is implemented to process graphics data in parallel, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent implements pipelining by performing preliminary actions at each stage of the processing pipeline - data is pre-processed and prepared at earlier stages before being passed to subsequent stages. This allows multiple data elements to be processed simultaneously at different pipeline stages, increasing throughput without requiring each processing element to handle complete operations sequentially, thereby achieving high productivity with controlled complexity through staged processing
Data Source
AI summary
One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.