Latency-Tolerant Microprocessor Queue Architecture
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Solution Overview
Problem
Computer processor architectures face limitations in increasing instructions per cycle due to memory access stalls, leading to inefficiencies in instruction execution and power consumption, particularly in portable devices where power conservation is crucial.
Innovation Solution
Implementing a superscalar microprocessor architecture with multiple load queues that allow instructions to execute in-order within their queues while enabling out-of-order execution across queues, using a combination of in-order and out-of-order instruction handling to manage dependencies and cache misses effectively, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are executed in-order, then dependency correctness is maintained, but memory access stalls reduce instructions per cycle
Solution Approach 1:
The patent segments instructions into different queues (load queue, store queue, integer queue) based on their memory access characteristics. This allows independent execution of instructions in different queues without waiting for memory stalls, while maintaining in-order execution within each queue for dependency correctness.
Solution Approach 2:
The patent implements dynamic queue selection where instructions are routed to different execution queues based on their latency characteristics and dependency requirements. The system dynamically adjusts which queue an instruction enters based on real-time execution conditions, optimizing both productivity and dependency management.
2Productivity
If instructions are issued out-of-order, then instructions per cycle increases, but stalled instructions block independent instructions from execution
Solution Approach 1:
The patent divides instructions into multiple queues (load queue for memory accesses, store queue for stores, integer queue for arithmetic operations). Each queue executes its instructions in-order, but instructions from different queues can execute out-of-order globally. This segmentation prevents stalled instructions from blocking independent instructions while maintaining dependency correctness within each queue.
3Productivity
If multiple out-of-order dependent instructions fill the queue, then instruction-level parallelism increases, but queue overflow blocks execution
Solution Approach 1:
The patent segments instructions into different queues based on their dependency characteristics and execution latency. This segmentation allows the system to maintain high instruction-level parallelism by executing independent instructions in parallel across different queues, while avoiding queue overflow by routing dependent instructions to appropriate queues where they can be executed in-order after their dependencies complete.
Data Source
AI summary
An instruction unit provides instructions for execution by a processor. A decode unit decodes instructions received from the instruction unit. Queues are coupled to receive instructions from the decode unit. Each instruction in a same queue is executed in order by a corresponding execution unit. An arbiter is coupled to each queue and to the execution unit that executes instructions of a first instruction type. The arbiter selects a next instruction of the first instruction type from a bottom entry of the queue for execution by the first execution unit.