Cross-Point Memory Current Pulse Generation via Selection Transistor Gate Control
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Solution Overview
Problem
Conventional cross-point memory devices face challenges in generating narrow, high-amplitude current pulses for reset operations due to significant resistance and parasitic capacitance in the path from dedicated current mirror circuits to memory cells, limiting edge rates and increasing die size.
Innovation Solution
The technique involves controlling the gate voltage of a selection transistor to generate program current pulses without dedicated current mirror circuits, utilizing inherent capacitances near the memory cell to produce narrower pulses with faster rise and fall times, and reducing die size by eliminating the need for dedicated current generator circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated current mirror circuits are used to generate program current pulses, then current amplitude control is achieved, but pulse width is excessive and edge rate is limited due to resistance and parasitic capacitance
Solution Approach 1:
The patent extracts the current pulse generation function from dedicated current mirror circuits and relocates it to the word line driver circuit. This eliminates the need for separate current mirror circuits, reducing device complexity while improving edge rate by removing the resistance and parasitic capacitance bottlenecks associated with dedicated current paths.
Solution Approach 2:
The patent merges the current pulse generation function into the word line driver circuit. By combining selection transistor control with current pulse generation in a single integrated circuit, the design achieves both amplitude and width control without requiring separate dedicated current mirror circuits, thereby reducing overall device complexity.
2Area of stationary object
If dedicated current mirror circuits are used, then current control is possible, but die size increases
Solution Approach 1:
The word line driver circuit is designed to perform multiple functions: it selects memory cells through transistor control and simultaneously generates the required program current pulses. This multi-functionality eliminates the need for separate dedicated current generator circuits, thereby reducing die size while maintaining current control capability.
Solution Approach 2:
The current pulse generation function is extracted from dedicated current mirror circuits and integrated into the word line driver. This extraction eliminates redundant circuitry and reduces the overall die area required for current generation functionality.
3Duration of action of moving object
If conventional current mirror circuits are used, then current amplitude can be controlled, but pulse width cannot be sufficiently narrowed
Solution Approach 1:
The patent employs dynamic control of the selection transistor gate voltage to precisely regulate the duration of current flow. By dynamically adjusting the gate voltage timing, the system generates narrow current pulses with controlled width, overcoming the limitations of conventional current mirror circuits that cannot produce sufficiently narrow pulses.
4Use of energy by moving object
If dedicated current mirror circuits are used, then current generation is reliable, but energy consumption increases
Solution Approach 1:
By merging current pulse generation into the word line driver circuit, the patent eliminates redundant circuit operations. The integrated design generates current pulses using the existing word line driver transistors and capacitances, avoiding the additional energy consumption associated with separate dedicated current mirror circuits while maintaining reliable current delivery to memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the generation of narrower current pulses with faster edge rates and reduced energy usage, effectively addressing the limitations of conventional methods and improving memory operation efficiency.
Implementation Method 1
charge sharing between capacitance at the source and drain terminals of the transistor
Implementation Method 2
a memory cell that switches between a high resistance state and a low resistance state
Data Source
Figure 1~2
Figure 3A
Figure 3B
AI summary
A program current pulse (e.g., reset or set pulse) for a cross-point memory cell can be generated with improved efficiency and effectiveness by controlling the voltage applied to a selection transistor near the memory cell to increase current through the memory cell. In one example, a method involves applying a first voltage to a gate of a selection transistor coupled between the memory cell and a first supply voltage and transitioning the first voltage applied to the gate of the selection transistor to a second voltage. The transition from the first voltage to the second voltage causes an increase of current through the memory cell due to a charge sharing event between capacitances at the terminals of the selection transistor. The current path through the memory cell can then be disabled to terminate the program current pulse. The timing and magnitude of the control signals can be controlled to achieve the desired current pulse width and amplitude.