Cross-Point Memory With Self-Aligned Nanowire Elements
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Solution Overview
Problem
As memory devices shrink in size, conventional memory devices face challenges in producing smaller cell sizes due to misalignment issues and additional processing steps required for memory element formation, which can lead to inefficiencies and errors in data storage and retrieval.
Innovation Solution
A memory device with a memory array that uses self-defined memory elements formed by nanowires, where regions with variable resistance materials are configured to store information based on resistance values, eliminating the need for separate diodes or rectifying components and allowing for self-alignment, thus reducing processing steps and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional memory elements with separate diodes and rectifying components are used, then memory cell functionality is achieved, but device complexity and processing steps increase
Solution Approach 1:
The patent combines multiple functions (memory element, diode, and rectifying component) into a single nanowire structure. The nanowire inherently provides both memory functionality through variable resistance regions and diode functionality through its asymmetric contact configuration, eliminating the need for separate rectifying components and reducing overall device complexity
Solution Approach 2:
The nanowire structure serves multiple functions simultaneously: it acts as the memory element storage medium, provides diode-like rectifying behavior through asymmetric contacts, and enables self-alignment. This multi-functionality reduces the number of separate components needed and simplifies the overall memory cell design
2Quantity of substance
If memory cell size is reduced to increase density, then memory device density improves, but misalignment issues and manufacturing precision requirements worsen
Solution Approach 1:
The nanowire structure with asymmetric contacts enables self-alignment of the memory element. The variable resistance region forms naturally at specific locations along the nanowire based on the contact asymmetry, eliminating the need for precise external alignment processes and reducing manufacturing precision requirements as cell size decreases
Solution Approach 2:
The patent transitions from planar memory cell layouts to a vertical nanowire-based structure. By utilizing the vertical dimension and forming variable resistance regions along the length of the nanowire, the design achieves higher density while maintaining manufacturing feasibility through self-aligned formation processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher memory device density, reduces misalignment issues, and enhances scalability by using self-defined memory elements that store information based on resistance values, improving data storage efficiency and reducing operational complexities.
Implementation Method 1
regions with variable resistance materials are configured to store information based on resistance values
Data Source
AI summary
Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described.