Cross-Point Memory Sidewall Protection During Etching

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Solution Overview

Problem

The fabrication of cross-point memory arrays faces challenges such as damage and cross-contamination of sidewalls during etching processes, leading to undesirable effects on the final device characteristics and yield.

Innovation Solution

A method involving forming a memory cell material stack with protective liners on sidewalls before completing the etching process, using dry etching techniques like reactive ion etching, to prevent contamination and damage, and subsequently removing the liners to expose the surfaces for further processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If etching is performed to form stacked memory structures, then memory elements are successfully patterned, but sidewalls of the stacked structure become damaged and contaminated

Engineering Contradiction:
Improvepatterning precisionVSAvoidsidewall damage and contamination
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A protective liner material is deposited on the sidewalls of the stacked structure to act as an intermediary barrier during etching. This liner prevents direct contact between the etchant and the sidewalls, thereby preventing damage and contamination while allowing the etching process to proceed effectively

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective liner is deposited on the sidewalls before the etching process begins. This preliminary protective action ensures that when etching occurs, the sidewalls are already shielded, preventing damage and contamination from occurring in the first place

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes sidewall damage and contamination, enhancing the fabrication yield and electrical performance of the memory cells by protecting the sidewalls during etching and allowing for precise control over the etching process.

Implementation Method 1

depositing a protective liner material on the sidewalls of the stacked structure

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

using dry etching techniques like reactive ion etching

Methodology Applied
Scientific EffectReactive Ion Etching:

Data Source

PatentUS11600665B2Cross-point memory and methods for fabrication of same
Publication Date: 2023.03.07 MICRON TECHNOLOGY INC
  • US11600665B2 patent drawing
  • US11600665B2 patent drawing
  • US11600665B2 patent drawing

AI summary

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.