Crossbar Non-Volatile Memory Demultiplexing via Multispacer Nano-Wires
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Solution Overview
Problem
Existing crossbar non-volatile memory technologies face challenges in scaling down due to limitations in active dielectric layers and stress-induced leakage currents, leading to reduced memory integration density and performance, particularly in accessing and addressing nano-scale memory cells effectively.
Innovation Solution
A method and device utilizing a multispacer structure with progressively reduced nano-wires and modulated doping concentrations to enable selective addressing and control of memory cells through adjustable voltage thresholds, allowing for efficient demultiplexing and reading of memory states in a reduced area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the transistor is reduced photo-lithographically to increase memory integration density, then the number of cells per area increases, but the scalability of active dielectric layers is limited by cell charge retention and stress induced leakage current
Solution Approach 1:
The patent segments the memory cell into a crossbar architecture with separate word lines and bit lines, allowing independent control and access to individual memory cells through selective activation of transistor gates, thereby maintaining charge retention while enabling high-density integration
Solution Approach 2:
The patent transitions from planar transistor scaling to three-dimensional crossbar structure with vertical interconnects and stacked memory cells, enabling increased integration density without proportionally reducing dielectric layer thickness that would compromise charge retention
2Quantity of substance
If the oxide thickness is scaled to 6-7 nm to reduce cell size, then memory integration density increases, but reading performance becomes worse
Solution Approach 1:
The patent introduces sense amplifiers and read assistance circuits as intermediary components that enhance the signal detection capability for weak current signals generated by thin oxide tunneling, thereby maintaining reading performance even at reduced oxide thickness of 6-7 nm
Solution Approach 2:
The patent dynamically adjusts read voltage parameters and pulse widths based on the specific memory cell characteristics and desired read margin, optimizing the balance between reading performance and cell disturbance while operating at scaled oxide thickness
3Ease of manufacture
If crossbar memory is manufactured by conventional lithography tools, then manufacturing process is simpler, but the pitch of arrays is limited to few tens of nano-meters without electron-beam lithography
Solution Approach 1:
The patent employs preliminary spacer formation and self-aligned patterning processes where mandrels are first deposited and patterned, then spacers are formed by conformal deposition and anisotropic etching, automatically defining the final array pitch with precision independent of lithography resolution limits
Solution Approach 2:
The patent replaces direct lithographic pattern definition with a deposition-and-etching based self-aligned patterning process, where the spacer width is controlled by film thickness deposition precision rather than optical resolution, achieving sub-10nm pitch with conventional lithography tools
4Quantity of substance
If multi-spacer structure is used to reduce nano-wire size for higher density, then memory integration density increases, but the complexity of selective addressing and control of memory cells increases
Solution Approach 1:
The patent segments the control function into separate control circuits for word lines and bit lines, with independent decoding and driving circuits that can selectively activate specific lines without interfering with others, thereby managing the complexity of addressing in high-density multi-spacer crossbar structures
Solution Approach 2:
The patent designs control circuits that can perform multiple functions including address decoding, signal routing, and timing control within integrated circuits, reducing the overall device complexity by consolidating control functions rather than requiring separate dedicated circuits for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-resolution, high-density demultiplexing of crossbar non-volatile memory with reduced integration losses, enabling efficient addressing and control of memory cells while maintaining high bit density, thus overcoming the limitations of existing technologies.
Implementation Method 1
The method comprises the steps of: providing a cross-bar non-volatile memory including a first array of parallel nano-wires and a second array of parallel nano-wires orthogonal to the first array, wherein the nano-wires are formed by the spacers of a multispacer structure... a region of the array running under the first electrode and a region of the array running under the second electrode have been doped in order to form respectively a plurality of FET transistors
Implementation Method 2
A method and device utilizing a multispacer structure with progressively reduced nano-wires and modulated doping concentrations to enable selective addressing and control of memory cells through adjustable voltage thresholds
Data Source
AI summary
A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.