Nanoinformatics TRIZ Cases

A patterned chemical epitaxy template guides self-assembled block copolymers using a primer layer with specific polymer moieties.

A carbon nanotube field effect transistor uses a high-k gate dielectric to minimize parasitic capacitance.

Force sensors measure applied load on the neutral plane of an imprint template, compensating for actuator alignment errors and structural distortions.

A microelectronic device architecture uses a semiconductor layer wrapping around source and drain regions to form large contact surfaces.

A titanium nitride lower electrode enhances adherence to the organic photoelectric conversion layer.

Sacrificial silicon germanium fills cavities between nanosheets, enabling precise spacer formation that reduces gate-to-source/drain capacitance.

Atomic force microscope nanomachining tip creates high aspect ratio nanostructures via alternating cuts, resolving photomask repair precision limits.

A magneto-electric spin-FET uses voltage-controlled interface magnetization to polarize the channel conductor.

Multispacer nano-wires with modulated doping enable selective addressing in crossbar non-volatile memory arrays.

A vertical gate structure uses carbon nanotubes and graphene to reduce channel resistance in semiconductor devices.

Integrating a diffraction grating with varying pitch into the magnetic layer allows accurate disk alignment without adding separate manufacturing steps.

Segmented gate lengths in a hybrid FinFET-nanowire structure resolve the trade-off between packing density and electrostatic control, reducing leakage current.

A chemical amplification resist composition uses acid-decomposable resin groups to enable precise nanoimprint mold preparation.

Dynamic programming pulses adjust resistive states based on measured current, preventing deep set data loss during reset operations.

An in situ treatment replenishes ablated layers and covers contaminants on EUV optics, maintaining reflectivity without operational interruptions.

Self-assembled nanodielectrics enable high-performance III-V field effect transistors with organic gate dielectric materials.

Patterned substrate regions guide evaporating droplets to orient nanostructures, reducing material waste and improving manufacturing precision.

Segmented polymer compound with heterocyclic units boosts short-circuit current and voltage, resolving efficiency-complexity trade-offs.

Dynamic back surface polishing removes residual films and scratches to prevent lithography distortion while maintaining productivity.

Chemisorption of a modifier onto a surface passivation layer creates a nanoparticle covering layer that prevents galvanic effects during wet etching.

A method forming superimposed nanowires using sacrificial gates and insulating spacers to define source and drain regions.

Carbon interface layer on semiconductor channel pattern prevents germanium diffusion, maintaining flatness and controlling short channel effects.

A plasmon superlens template supports surface plasmon oscillations to produce subwavelength features on photosensitive material.

Coactive gate-island coupling and barrier separation in a tunneling transistor enable 3D memory stacking without high temperature processes.

Multi-layer mask segmentation defines semiconductor columns with varying spacing, increasing transistor density while managing gate capacitance.

Chemical vapor deposition of tungsten and germanium gases creates compound films with adjustable optical energy gaps, overcoming substrate melting limits.

Segmented power rails with doping regions transfer voltage efficiently, preventing electromigration failures in dense integrated circuits.

An insulating capping layer on the upper gate material enables self-aligned gate-cut formation in stacked transistor devices.

Clamped carbon nanotube gate merges resonator and transistor functions to resolve high dynamic resistance, enabling 100 MHz to 100 GHz signal processing.

A diode structure uses carbon nanotubes to create an organic composite plate with adjustable band gap properties.

Nanotube fabrics emit heat via Joule heating to trigger phase transitions in chalcogenide materials, resolving fabrication complexity of individual nanotubes.

Copper sulfide layers strengthen ionic bonding to increase erase activation energy and prevent data loss.

Epitaxial GeSn:B regions lower contact resistance in scaled nanowire transistors, maintaining high mobility without increasing process complexity.

A semiconductor film deposited in a recess undergoes differential removal to retain the bottom segment while stripping the sidewall segment.

A semiconductor device uses a spacer below the gate structure to protect the field insulating layer during fabrication.

Actuator device applies orthogonal force to substrate holder, preventing die tilting and drifting that reduces edge yield on non-flat substrates.

Early top source/drain epitaxy aligns junctions with gate structures, reducing underlap variability in vertical fin transistors.

An oxygen-rich protective layer on a mask blank thin film reduces etching bias and resist recession during chlorine-based dry etching.

A patterned substrate guides magnetic grain growth via non-magnetic segregant boundaries, reducing superparamagnetic noise and enhancing data density.

Patterned growth substrate defines device architecture via shadow mask deposition.

Segmented semiconductor structure with adjustable dopant concentration resolves trade-offs between threshold voltage control and charge carrier mobility.

Metallic or oxide coated polymer templates reduce static charges and separation force, extending durability for high-throughput manufacturing.

Merging the gate contact structure with the gate structure eliminates parasitic capacitance and short-circuit risks in high aspect ratio devices.

Segmenting the channel with a recessed body resolves threshold voltage control issues while maintaining high on-current.

Silole-containing copolymers shift absorption toward near-infrared wavelengths to enhance current generation in photovoltaic cells.

A semiconductor arrangement uses segmented mask regions to form vertical columns with controlled dimensions.

Stacked wire patterns with varying widths reduce short channel effect while maintaining current control capability.

Conformable transfer device moves printable semiconductor elements onto plastic substrates, enabling high field effect mobilities without thermal damage.

Vertical stacking of channel patterns with concave source/drain regions increases strain to resolve size-reliability trade-offs.