Semiconductor Device With Stacked Wire Patterns
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the short channel effect (SCE) and effectively controlling current flow, particularly due to limitations in scaling and current control capabilities.
Innovation Solution
The semiconductor device incorporates a design with multiple wire patterns of varying widths and numbers, stacked to control current flow and reduce SCE by optimizing the width and number of wire patterns in specific directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length is increased to reduce short channel effect, then the SCE is suppressed, but the current control capability deteriorates and device area increases
Solution Approach 1:
The patent transitions from planar 2D channel to three-dimensional 3D channel structure by stacking multiple wire patterns vertically. This dimensional change allows the gate to control the channel from multiple sides (top, bottom, and sidewalls), achieving effective SCE suppression without increasing gate length, thereby maintaining excellent current control capability
Solution Approach 2:
The gate electrode is designed to surround the wire pattern channel in a nested configuration, with the gate wrapping around the channel from multiple directions. This nested structure enables the gate to control the channel effectively without requiring increased gate length, resolving the contradiction between SCE suppression and current control
2Reliability
If the gate length is increased to reduce short channel effect, then the SCE is suppressed, but the device area increases
Solution Approach 1:
By stacking wire patterns vertically to form 3D channels, the patent achieves SCE suppression through enhanced gate control in three dimensions rather than increasing gate length horizontally. This vertical stacking approach reduces the lateral device area while maintaining reliability
Solution Approach 2:
The channel is segmented into multiple stacked wire patterns, each controlled by the gate from multiple sides. This segmentation allows efficient use of vertical space, reducing the horizontal device area required while achieving effective SCE suppression through the combined control of multiple channel segments
3Productivity
If multiple wire patterns with different widths are stacked to control current, then current control capability is improved, but device complexity increases
Solution Approach 1:
Different wire patterns in the stack are assigned different widths tailored to specific current control requirements. Each wire pattern's width is optimized for its intended function, allowing precise local control of current characteristics without requiring complex external circuitry
Solution Approach 2:
The stacked wire pattern structure serves multiple functions simultaneously: it provides current control through varied widths, achieves SCE suppression through 3D gate control, and enables device scaling. This multi-functionality reduces the need for additional separate structures, thereby managing complexity
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.