Microelectronic Device With 3D Semiconductor Wrapping For Contact Resistance
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Solution Overview
Problem
Conventional microelectronic devices using 2D materials face challenges with small contact surfaces between the conduction channel and the source and drain regions, leading to significant contact resistances and potential barriers at the interface, which hinder performance and scalability.
Innovation Solution
A microelectronic device architecture is proposed with a semiconductor layer comprising second regions that extend against the flanks of the source/drain regions, forming a large contact surface and eliminating the need for silicon portions, thereby reducing contact resistances and allowing for homogeneous 2D material growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If side contact configuration is used to overcome deposition constraints, then ease of manufacture is improved, but contact surface area is reduced leading to increased contact resistance
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional contact by having the semiconductor layer wrap around the source/drain regions. This dimensional change increases the contact surface area from a single interface to multiple interfaces (top, bottom, and lateral surfaces), thereby reducing contact resistance while maintaining the side contact manufacturing advantage
Solution Approach 2:
The semiconductor layer is configured to wrap around and enclose the source/drain regions, creating a nested structure where the channel material surrounds the contact regions. This nesting maximizes the interfacial contact area between the semiconductor and source/drain, enabling large contact surfaces without compromising ease of manufacture
2Ease of manufacture
If silicon portions are used to deposit 2D material, then ease of manufacture is improved, but potential barriers are created at the interface
Solution Approach 1:
The patent removes the silicon portion material from the final device structure after it has served its purpose as a deposition substrate. The 2D material is transferred from the silicon sacrificial layer to the final device, eliminating the silicon-2D material interface and its associated potential barriers while retaining the manufacturing benefits of using silicon as a temporary support
Solution Approach 2:
The silicon portion acts as an intermediary or sacrificial substrate during manufacturing. It facilitates the deposition and handling of 2D material during fabrication, then is removed to prevent it from creating harmful interface effects in the final device, thus serving a temporary but essential manufacturing function
3Productivity
If device dimensions are reduced for miniaturization, then productivity is improved, but contact surface area is reduced leading to increased contact resistance
Solution Approach 1:
As device dimensions are reduced, the patent compensates for the loss of contact area by utilizing three-dimensional wrapping geometry. The semiconductor layer extends around the source/drain regions in multiple dimensions, maintaining adequate contact surface area even when the overall device footprint is minimized for high-density integration
Solution Approach 2:
The thin film nature of the 2D semiconductor material allows it to conformally wrap around the source/drain regions, maximizing contact area within the available space. This flexible thin-film approach enables adequate contact surfaces even in highly miniaturized devices where planar contact area would be insufficient
Data Source
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AI summary
A microelectronic device (100) comprising: - a semiconductor layer (120) of which several first zones (122) are superimposed and form a channel; - an electrostatic control gate (110) and a gate dielectric layer (112) or a ferroelectric memory layer (112) of which portions are each disposed between a portion (106, 108) of the gate and one of the first zones; - dielectric spacers (114) disposed against flanks of the gate; - source (116) / drain (118) regions electrically coupled to the first zones by second zones (124) of the semiconductor layer extending between the source/drain regions and the spacers, and/or between a substrate (102) and each of the source/drain regions; and in which the second zones are not disposed directly against the gate and form, with the first zones, a continuous layer.