Semiconductor Column Density via Multi-Mask Segmentation
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Solution Overview
Problem
Current semiconductor arrangements face challenges in efficiently forming semiconductor columns with precise spacing and density, which affects the performance and density of transistors, particularly in vertical gate all around (VGAA) transistors.
Innovation Solution
The method involves forming multiple mask regions with specific materials like SiO2 and Si3N3, patterned to create openings and layers, followed by planarization and etching to define semiconductor columns with varying distances and orientations, increasing the density of semiconductor columns per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor manufacturing methods are used, then manufacturing simplicity is maintained, but semiconductor column density and precision are insufficient
Solution Approach 1:
The patent divides the formation process into multiple stages using different mask regions (first mask region with SiO2, second mask region with Si3N4) to precisely control semiconductor column positions. Each mask region is patterned separately to define specific column groups, enabling precise spacing control that cannot be achieved with conventional single-step methods.
Solution Approach 2:
The patent introduces vertical layering with multiple mask regions at different heights and compositions. The first mask region (SiO2) and second mask region (Si3N4) are formed in stacked configurations, allowing three-dimensional control over column formation. This multi-layer masking approach enables precise column density control by selectively exposing different areas at different stages.
2Quantity of substance
If semiconductor column density is increased, then power per unit area increases, but gate capacitance control becomes more difficult
Solution Approach 1:
The patent applies different mask materials (SiO2 for first mask region, Si3N4 for second mask region) with different etch selectivities to different spatial zones. This allows local control over column formation - some areas receive full exposure while others are protected, enabling precise control of column density in different regions to optimize both power density and gate capacitance characteristics.
Solution Approach 2:
The first mask region is formed and patterned before the second mask region, creating a hierarchical control structure. The preliminary mask defines coarse column positions, while the subsequent mask refines the pattern to achieve final precise spacing. This sequential approach enables better control over gate capacitance by progressively defining column locations.
3Quantity of substance
If multiple mask regions with different materials are used, then semiconductor column density increases, but manufacturing process complexity increases
Solution Approach 1:
The multi-layer mask structure serves multiple functions: the first mask region (SiO2) defines initial column positions and provides spacing control, while the second mask region (Si3N4) refines the pattern and protects specific areas. Each layer performs distinct functions that collectively achieve high column density with controlled gate capacitance, making the complex process worthwhile for the performance gains.
Solution Approach 2:
The patent changes material parameters (using SiO2 with different etch selectivity than Si3N4) to enable selective removal and exposure during the formation process. By utilizing materials with distinct chemical and physical properties, the process achieves precise column definition through differential etching, where each mask material responds differently to etch conditions, enabling fine-tuned control over column formation.
Data Source
AI summary
A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.