Semiconductor Device With Stacked Channels And Air Gaps
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Solution Overview
Problem
The scale-down of MOS-FETs in semiconductor devices leads to deterioration in operational properties, necessitating improved designs to enhance electric characteristics and reliability.
Innovation Solution
A semiconductor device is designed with an insulating layer, vertically stacked channel semiconductor patterns, a gate electrode crossing these patterns, and source/drain regions with concave bottom surfaces and air gaps between the insulating layer and the source/drain regions, which allows for increased strain on the semiconductor channel and improved electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically stacked 3D channel semiconductor patterns. This dimensional change allows the device to maintain smaller footprint area while preserving operational properties through increased channel length in the vertical direction, effectively resolving the contradiction between device size reduction and operational performance maintenance
Solution Approach 2:
Multiple channel semiconductor patterns are stacked vertically within a compact space, creating a nested multi-layer structure. This nesting approach enables the device to achieve both small overall dimensions and sufficient channel length for reliable operation, as the channels are arranged in layers rather than requiring lateral expansion
2Reliability
If channel length is increased to improve operational properties, then electric characteristics improve, but device area increases
Solution Approach 1:
The channel length is extended vertically through stacked channel semiconductor patterns rather than horizontally. This allows the effective channel length to increase for improved electric characteristics while the device footprint area remains small, as the additional channel length is achieved in the vertical dimension perpendicular to the substrate plane
3Device complexity
If source/drain regions are positioned closer to insulating layer to reduce device height, then device complexity is reduced, but strain on channel semiconductor patterns decreases
Solution Approach 1:
The source/drain regions are designed with asymmetric positioning relative to the channel semiconductor patterns, creating offset configurations that generate mechanical strain on the channel. This asymmetric arrangement allows the regions to be positioned at optimal locations that simultaneously achieve reduced device height and maintain sufficient strain for improved carrier mobility
Solution Approach 2:
Strain is locally enhanced at specific positions where source/drain regions are positioned adjacent to or overlapping with channel semiconductor patterns. By concentrating strain-inducing structures at critical locations rather than uniformly distributing them, the design achieves effective channel strain with minimized overall device height and complexity
Data Source
AI summary
A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.