Semiconductor Channel Pattern Carbon Interface Layer
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Solution Overview
Problem
The demand for miniaturization of semiconductor devices to achieve high capacity and integration poses challenges in preventing short channel effects and enhancing operating current, particularly in finFET structures where maintaining effective channel lengths and gate widths is crucial.
Innovation Solution
A semiconductor device with a channel pattern and gate pattern on a substrate, where an interface layer containing carbon is formed on the surfaces of the channel pattern, helping to prevent germanium diffusion and enhance channel flatness, and a method involving sacrificial films and epitaxial growth to manufacture this structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel pattern is miniaturized to increase integration density, then the degree of integration increases, but short channel effects worsen and channel flatness decreases
Solution Approach 1:
A carbon-containing interface layer is introduced as an intermediary between the channel pattern and gate pattern. This interface layer acts as a mediator that prevents germanium diffusion from the channel to the gate, maintains channel flatness, and controls short channel effects while allowing the channel to be miniaturized for higher integration density
Solution Approach 2:
The interface layer is formed as a composite structure containing carbon, which may include multiple sub-layers with different compositions. This composite material approach allows optimization of both diffusion prevention and flatness maintenance functions simultaneously
2Productivity
If the channel pattern is miniaturized to increase integration density, then the degree of integration increases, but channel flatness decreases
Solution Approach 1:
The carbon-containing interface layer serves as a mediator that maintains channel flatness during miniaturization. It provides a stable interface that prevents material diffusion and maintains the geometric precision of the channel structure even at reduced dimensions
Solution Approach 2:
The interface layer is formed in advance before the gate pattern is created. This preliminary action establishes a protective and planarizing layer that maintains channel flatness before subsequent processing steps, preventing degradation of geometric precision during device fabrication
3Power
If germanium is used in the channel pattern to enhance operating current, then the operating current increases, but germanium diffusion to the gate pattern worsens short channel effects
Solution Approach 1:
The carbon-containing interface layer acts as a diffusion barrier intermediary between the germanium channel and the gate. It allows the high-operating-current benefits of germanium to be realized while preventing germanium atoms from diffusing into the gate region, which would otherwise degrade device performance through short channel effects
Solution Approach 2:
The harmful diffusion of germanium is extracted or blocked by the interface layer, separating the beneficial electrical properties of germanium from its harmful diffusion behavior. The interface layer selectively prevents germanium migration while maintaining the operational advantages of germanium channels
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases channel flatness and prevents germanium diffusion, ensuring reliable operation and high integration density in semiconductor devices.
Implementation Method 1
forming an interface film on the sacrificial film such that the interface film includes carbon
Implementation Method 2
forming a channel film on the interface film
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.