Vertical Transport FET Self-Aligned Top Junction

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Solution Overview

Problem

Existing vertical transport field effect transistors (VT FETs) face challenges in aligning top source/drain junctions with gate structures, leading to variability in junction positions such as underlap or overlap, which affects device performance.

Innovation Solution

The method involves forming a vertical fin on a substrate, thinning it to create a thinned portion and tapered upper and lower portions, depositing a gate dielectric layer with angled portions on these tapered sections, and applying a work function metal layer with a thinner section adjacent to the upper tapered portion, followed by an encapsulation layer to control junction positions and reduce variability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional alignment methods are used for top source/drain junctions with gate structures, then manufacturing process is simpler, but junction position variability (underlap/overlap) increases affecting device performance

Engineering Contradiction:

Improvejunction position alignmentVSAvoidfin structure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The vertical fin is segmented into three distinct regions: a thinned portion, a tapered upper portion, and a tapered lower portion. This segmentation allows each region to serve a specific function in controlling the top source/drain junction alignment, with the thinned portion providing a precise alignment reference and the tapered portions enabling controlled epitaxial growth

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The fin is pre-shaped with thinned and tapered portions before depositing the gate dielectric layer and forming the top source/drain junctions. This preliminary structuring establishes the alignment geometry in advance, ensuring that subsequent epitaxial growth and junction formation occur at precisely controlled positions relative to the gate structure

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If vertical fin is thinned to improve junction alignment, then alignment precision improves, but fin structural integrity may be compromised

Engineering Contradiction:

Improvejunction alignment precisionVSAvoidfin structural strength

Core Design Contradiction:

Manufacturing precisionVSStrength

Solution Approach 1:

The fin structure exhibits local quality variations with different regions having different thicknesses and geometries. The thinned portion provides precise alignment geometry while the adjacent tapered portions and broader base regions maintain structural support, allowing the fin to achieve both precision and strength through spatially differentiated properties

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11239360B2Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy

Publication Date: 2022.02.01 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.