Stacked FET Capping Layer for Self-Aligned Gate-Cut
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Solution Overview
Problem
The challenge in developing three-dimensional transistor structures is to effectively form gate-cuts between stacked transistors without damaging the channel layers, especially as the pitch of gate and nanosheets continues to down-scale.
Innovation Solution
The implementation of a self-aligned gate-cut technique, where an insulating capping layer is formed on the upper gate material, helps in spacing the gate-cut adequately from adjacent transistors, reducing the risk of damage even if the gate-cut is misaligned.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-cut is formed between stacked transistors to separate adjacent transistors, then transistor isolation is improved, but risk of damage to channel layers increases
Solution Approach 1:
An insulating capping layer is formed on the upper gate material before forming the gate-cut. This preliminary action creates a protective structure that prevents etch damage to the channel layers when the gate-cut is subsequently formed, while still allowing effective transistor isolation.
Solution Approach 2:
The insulating capping layer acts as an intermediary between the upper gate material and the gate-cut etch process. It provides a protective barrier that allows the gate-cut to be formed without directly exposing the channel layers to the etching process, thus isolating transistors while protecting sensitive structures.
2Productivity
If pitch of gate and nanosheets is down-scaled to increase transistor density, then device integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The self-aligned gate-cut technique uses the upper gate material and insulating capping layer structure itself as the alignment reference for forming the gate-cut. This self-service approach eliminates the need for separate alignment markings or complex lithography steps, enabling precise gate-cut formation even as pitch is down-scaled to increase transistor density.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Stacked field-effect transistor, FET devices are provided. A stacked FET device includes a lower FET (Tb) having lower channel layers (120b) and a lower gate material (170b) (e.g. a work-function metal, WFM, layer) that is between the lower channel layers (120b). The stacked FET device includes an upper FET (Ta) that is on top of the lower FET (Tb). The upper FET (Ta) has upper channel layers (120a) and an upper gate material (170a) (e.g. a WFM layer) that is between the upper channel layers (120a). Moreover, the stacked FET device includes an insulating capping layer (180) that is on the upper gate material (170a). Related methods of forming stacked FET devices are also provided.