Cross-Point Memory Cell Layout for Scaling and RC Delay Control
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Solution Overview
Problem
The demand for high-integration semiconductor devices with improved electrical characteristics and reliability is challenging due to the reduction in widths and thicknesses of memory devices with a cross-point structure, leading to reduced electrical performance and reliability.
Innovation Solution
A method of manufacturing a memory device involves forming a preliminary selection device layer, middle electrode layer, and variable resistance layer on a substrate, followed by etching to create a cross-point array structure with specific width ratios and capping layers, and using insulation patterns with a lower dielectric constant to reduce RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the widths and thicknesses of memory devices are reduced for down-scaling, then integration density increases, but electrical characteristics and reliability deteriorate
Solution Approach 1:
The patent applies different width dimensions to different layers: the middle electrode layer has a first width, the variable resistance layer has a second width, and the selection device layer has a third width. This local differentiation allows optimization of electrical characteristics at each layer while maintaining overall high integration density through the cross-point structure.
Solution Approach 2:
The patent transitions from planar scaling to three-dimensional cross-point structure, where memory cells are formed at intersections of bit lines and word lines in multiple layers. This dimensional approach increases storage capacity without further reducing lateral dimensions, thereby maintaining electrical performance while improving integration density.
2Volume of moving object
If the widths and thicknesses of memory devices are reduced for down-scaling, then device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into distinct layers (middle electrode layer, variable resistance layer, selection device layer) with different width specifications. This segmentation allows independent optimization and control of each layer's dimensions, simplifying the manufacturing process and reducing alignment complexity despite the three-dimensional structure.
3Speed
If insulation patterns with lower dielectric constant are used, then RC delay is reduced improving speed, but manufacturing complexity increases
Solution Approach 1:
The patent changes the dielectric parameter of insulation patterns by selecting materials with lower dielectric constants. This parameter modification reduces RC delay and improves operation speed. The patent integrates this into the existing multi-layer fabrication process without requiring fundamentally new manufacturing techniques.
Data Source
AI summary
A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.